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DIGITAL 2 : EKT 221 RTL : Microoperations on a Single Register

DIGITAL 2 : EKT 221 RTL : Microoperations on a Single Register. Today’s Outline. Multiplexer-based transfers Transforming Block Diagram to Detailed Logic Shift Registers Shift Registers with Parallel Loads Shift Registers with Parallel Loads and Hold. Multiplexer-based transfer.

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DIGITAL 2 : EKT 221 RTL : Microoperations on a Single Register

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  1. DIGITAL 2 : EKT 221RTL : Microoperations on a Single Register

  2. Today’s Outline • Multiplexer-based transfers • Transforming Block Diagram to Detailed Logic • Shift Registers • Shift Registers with Parallel Loads • Shift Registers with Parallel Loads and Hold

  3. Multiplexer-based transfer

  4. Microoperations on a Single Register • Implement one or more microoperations with a single register as the destination of all primary results. • The single register may also serve as a source of an operand for binary and unary operations. • A simple technique using multiplexers for selection is introduced to allow multiple microoperations on a single register

  5. Multiplexer-Based Transfers • A register receives data transfers from more than 1 sources. • A dedicated multiplexer is used to select the wanted input • Example shows: • If K1=1, R0 receives data from R1. • If K1=0, R0 receives data from R2. K2 K1 R2 n=4 S R0 0 1 n=4 R1 2:1 MUX n=4

  6. Multiplexer-Based Transfers • How do we represent this in RTL form? • Written in if-then-else: If (K1=1) then (R0 R1), else if (K2=1) then (R0 R2). • Written in RTL: K2 K1 R2 n=4 S R0 K1:R0 R1, K1K2:R0 R2 0 1 n=4 R1 2:1 MUX n=4 Hardware connections from two source registers, R1 and R2, to one common destination register, R0. Selection between R1 and R2 must be based on the control variables K1 and K2.

  7. Analyse the diagram for input: *n.c : no change Multiplexer-Based Transfers K2 K1 R2 n=4 S R0 0 1 n=4 R1 2:1 MUX n=4

  8. K2 K1 Load K2 K1 2 to 1 MUX Load D0 D1 D2 D3 Q0 Q1 Q2 Q3 R2 R2 S Block Diagram n=4 A0 A1 A2 A3 Load S R0 R0 0 Q0 Q1 Q2 Q3 Y0 Y1 Y2 Y3 Load 1 n=4 B0 B1 B2 B3 R1 2:1 MUX CLK n=4 Q0 Q1 Q2 Q3 D0 D1 D2 D3 D0 D1 D2 D3 R1 Detailed Logic Transforming a Block Diagram into Detailed Logic

  9. Shift Registers

  10. Shift Registers move data laterally within the register toward its MSB or LSB position In the simplest case, the shift register is simply a set of D flip-flops connected in a row like this: Shift Registers *CP: a common clock pulse input that activates the shift

  11. Data input, In, is called a serial inputor the shift right input. Data output, Out, is often called the serial output. The vector (A, B, C, Out) is called the parallel output. Shift Registers Parallel Output Serial Output Serial Input

  12. Shift Registers • T0 is the register state just before the first clock pulse occurs • T1 is after the first pulse and before the second. • Initially unknown states are denoted by “?” • Complete the last three rows of the table

  13. Shift Registers with Parallel Load • The shift register shown earlier has no control input, thus data is always shifted on clock pulse. • How to make the shift registers more controllable? • E.g. shifts only on select positive clock edges. • Shift operation can be controlled through D inputs of the FFs, rather than through the clock inputs CP.

  14. By adding a mux between each shift register stage, data can be shifted or loaded If SHIFT is LOW, A and B are replaced by the data on DA and DB lines, else data shifts right on each clock. Shift Registers with Parallel Load Serial Input 2 to 1 MUX Dn A0 A1 IN Selector SHIFT

  15. Shift Registers with Parallel Loads and Hold Function Table for the Register of Fig 7-10 • But what if we want to hold to the current data, meaning no shift or no loading of new data? • The design must have 2 controls: • For the SHIFT • For the LOAD We use an AND gate to disabled the Load input, so we mark with don’t care condition

  16. In Register Transfer Language: Shift : Q sl Q, Shift Load : Q D 4-bit SHIFT REGISTER WITH PARALLEL LOAD AND HOLD OPERATION Control inputs • AND gates: • Enables the Shift operation • Enables the input data • Restores the contents of reg. when no operation 1 1 1 1 2 2 2 2 3 3 3 3 Figure 7-10 M. Morris Mano LOGIC AND COMPUTER DESIGN FUNDAMENTALS

  17. Shift Registers with Parallel Loads and Hold • S = 0, L = 0 : • AND3 in each stage is enabled • The output of each FF is applied to its own D input. • A +ve transition of CLK restores the contents of reg. • Output Qi is unchanged 1 2 3

  18. Shift Registers with Parallel Loads and Hold • S = 0, L = 1 : • AND2 in each stage is enabled • The input Di is applied to D input of corresponding FF. • Next +ve transition of CLK transfers the parallel input data into reg. • Output Qi = Di 1 2 3

  19. Shift Registers with Parallel Loads and Hold • S = 1 : • AND1 in each stage is enabled When +ve edge occurs on CLK: • Data from serial input SI to be transferred to FF Q0, • Output Q0 to be transferred to FF Q1, …and so on down the line. 1 2 3

  20. THANK YOU

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