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A/D Converters for SDR applications by : H. Mala M. Sajadieh A. Bakhtafrouz Isfahan University of Technology. Part 1. ADC systems for SDR applications By : Ahmad Bakhtafrouz. ADC Systems for SDR Digital Front-End. Performance Requirements. SNR and Sampling. Sigma-Delta ADCs.

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  1. A/D Converters for SDRapplicationsby : H. MalaM. SajadiehA. BakhtafrouzIsfahan University of Technology

  2. Part 1 ADC systems for SDR applications By : Ahmad Bakhtafrouz

  3. ADC Systems for SDR Digital Front-End • Performance Requirements • SNR and Sampling • Sigma-Delta ADCs • Time-Interleaved ADC Systems • High-Resolution ADC toward SDR Receivers • Introduction • Configurations of Superconductor-Based SDR Receivers • Development of ADCs • Commercial Capture Cards

  4. ADC Systems for SDR Digital Front-End Performance Requirements :

  5. ADC Systems for SDR Digital Front-End • An ADC operates directly at RF stage of a wideband receiver will need to • have a bandwidth of up to 5 GHz with sampling rate of at least twice the • signal bandwidth , which means up to 40 M sample/sec in the case of the • 802.11x wireless LAN system. • Because of the frequency bandwidth encountered by a wideband receiver • of the SDR, it is expected that ADC with at least 14-bit resolution will be • needed to detect weak desired channel in presence of strong neighboring • channels. • Dynamic range and bandwidth of ADCs is still needs major improvement • Using parallel ADCs of lower specifications are of great interest with active • research being conducted.

  6. ADC Systems for SDR Digital Front-End SNR and Sampling : • SNR directly affects the Bit Error Rate (BER) of the communication channel. • Maximum theoretical SNR of an ADC due to quantization noise (Nyquist rate) : • SNR = 6.02n + 1.76 dB • Every additional bit will add 6 dB of improvement . • One attractive technique to improve the SNR is oversampling. • In the oversampling technique, the sampling frequency is purposely increased beyond the Nyquist rate to spread the noise power over a wider frequency band. • SNR = 6.02n + 1.76 + 10log(fs/2fb) dB • Every factor-of-4 increment in the sampling frequency , the SNR is improved by 6dB which is equivalent to one additional bit.

  7. ADC Systems for SDR Digital Front-End Sigma-Delta ADC : • The Sigma-Delta ADC, provides additional noise shaping characteristics that is • more effective in improving the SNR. • Due to its internal operation, Sigma-Delta ADC act as a LPF to the signal but a • HPF to the quantization noise . • The actual noise shaping performance of the Sigma-Delta ADC depends on the • order of the modulator used inside the ADC. • SNR improvement of an Lth order Sigma-Delta • ADCs due to oversampling : • SNR = 6.02n + 1.76 + (20L+10)log(fs/2fb) dB • A 1st order Sigma-Delta ADC will provide 18dB • improvement which is equivalent to an additional • 3-bit resolution .

  8. ADC Systems for SDR Digital Front-End Time-Interleaved ADC Systems : • One technique that can be used to obtain the benefit of over sampling without • using ADC with exception sampling rate is to parallel multiple ADCs. • It is shown that mismatch of Gain ,Offset and clock skew between the ADCs will • degrade the SFDR and linearity of the overall system . • the offset mismatch between the • ADCs causes spectrums to appear • at multiples of the ADC sampling • frequency , while the gain mismatch • and clock skew cause spurious • spectrum to appear around the • multiples of the ADC sampling • frequency.

  9. ADC Systems for SDR Digital Front-End

  10. High-Resolution ADC toward SDR Receivers Introduction : • There is an increasing interest in radio receiver systems based on superconducting • technologies . • Analog BPFs utilizing high-temperature super-conductors have sharp skirt • characteristic and low insertion loss . • Superconducting single-flux-quantum (SFQ) logic circuits can operate at several • tens of GHz and have higher integration level than other ultra high-speed • semiconductor circuits . • A simple 1st order sigma-delta ADC is still insufficient to the SDR applications in • its performances even if a high-speed SFQ circuit is used.

  11. High-Resolution ADC toward SDR Receivers Configurations of superconductor-Based SDR receivers : • Bandpass ADC • Bandwidth 100MHz • SNR 100dB(16 bit) • Current sensitivity 100nA • Bandpass ADC • Bandwidth 20MHz • SNR 85dB(14 bit) • Current sensitivity 100nA

  12. High-Resolution ADC toward SDR Receivers Configurations of superconductor-Based SDR receivers : • Lowpass ADC • Bandwidth 20MHz • SNR 75-85dB (12-14 bit) • Current sensitivity lower • Several kinds of the SFQ ADCs have current sensitivity less than 100nA . Thus an • SFQ-ADC is the most promising candidate for the SDR receivers. • Lowpass ADC for the digital-IF receiver is a base for the other superconductor-based • SDR receivers. • A simple lowpass ADC based on the SFQ circuits is difficult to have both the broad • bandwidth and the high SNR required for the digital-IF receiver. • Quantizer-sampler-separated (QSS) ADC overcome this problem.

  13. High-Resolution ADC toward SDR Receivers Development of ADCs : QSS ADC : • the quantizer junction outputs an SFQ pulse train whose voltage is identical to • the total voltage VL+VR . • VR is an offset voltage so that the ADC may handle negative values of VL. • The first derivative of the analog signal is converted to the pulse period of the • PDM signal at the quantizer, and the period is measured at the sampler. • The junction Jq and DFF serve as a quantizer and a sampler .

  14. High-Resolution ADC toward SDR Receivers Development of ADCs : QSS ADC : • The SNR and sensitivity of the QSS ADC are improved by the interleave technique • in which the increased number of DFFs (samplers) are used to measure the time • difference between the adjacent pulses in the PDM signal more precisely. • In addition, a bandpass ADC is easily obtained by replacing the integrator with • a resonator. • Numerical analysis shows that the QSS ADC has higher sensitivity than the • sigma-delta ADC.

  15. High-Resolution ADC toward SDR Receivers Development of ADCs : Complementary Delta ADC : • The QSS ADC have a strict operating condition that the DC offset should keep • a constant value and it is difficult in the actual opration. • The output of the left modulator is multiplied by -1 and then added to the output • of the right modulator. • The ADC becomes insensitive to the common-mode signals containing the dc offset • and the noise mixed with that. • With 2nd order decimation filter and 8 sets of samplers, the SNR reaches 82dB • (13 bits) for a frequency band of 0.1-20 MHz.

  16. High-Resolution ADC toward SDR Receivers Development of ADCs : Complementary Delta ADC : • 3 sinusoidal signals around 20 MHz to the port of the DC offset Complementary ADC QSS ADC

  17. High-Resolution ADC toward SDR Receivers Development of ADCs : • SNR can be improved by increasing the number of the samplers. • In this calculation, we assume that the oversampling frequency is 20GHz and the • band of interest is ranging from 0.1-20 MHz. • The SNR is increased by about 6dB in every twice of the number of the samplers.

  18. Commercial Capture Cards High-Frequency Internal ADCs

  19. Commercial Capture Cards Card NVL-45 Price: $750  • two independent ADC channels the sampling rate of which is up to 60 MHz (each channel) • , resolution of the channels is12 bit (each channel) • sampling rate doubling  in single-channel (ping-pong) mode • input voltage ranges: +/-1 V, +/-2 V (program switching) • onboard memory: 4 Mb • 8-channels analog signals multiplexers (on the input of every ADC) • digital I/O ports (8 input and 8 output lines)  • PC connection through PCI bus, high speed of data exchange with the bus, plug-and-play • "oscilloscope" program is included in a set • drivers for Windows95/98/ME/NT/2000/XP, Linux 2.216 - 22 Red Hat 7.0 (Guinness) and • samples of VC programming 

  20. Commercial Capture Cards Card AD-PCI 12 Price: $1190 • two independent ADC channels resolution of which is12 bit, sampling rate of the channels • is 100 MHz • bandwidth: 100 MHz • one DAC channel (8 bit) • sampling rate: 100 MHz • PCI bus transmission speed: 100 MHz • drivers for Windows 95/98/ME/NT/2000/XP • sample of programming ("oscilloscope" program) with initial text in DELPHI

  21. Commercial Capture Cards Analog/digital conversion card for PCI - n10M6PCI Price: $994 • sampling rate: upto100 MHz (single-channel mode) • mode of sampling rate task-setting - fixed frequency of a quartz generator • bandwidth: (-3dB)- 50 MHz • ADC resolution: 8 bit • speed of conversion: 20 ns • onboard memory • two single-ended inputs for analog signals • analog inputs and external trigger inputs can be either single-ended or differential  

  22. Commercial Capture Cards Low-Frequency Internal ADCs

  23. Commercial Capture Cards Сard NVL03 Price: $198 • ADC: resolution 10 bit, 16 channels • voltage ranges +/-5V; +/-2,5V; +/-1,25V; +/-1V • conversion time: 30 ms • 16 double-ended channels of digital input and output • 3 ways of starting the ADC • the list of functions and testing programs "oscilloscope" are included in a set.

  24. Commercial Capture Cards ADC card PC-1202 Price $589  • PCI bus • 12-bit 110KHz A/D converter • PC-1002H/-1002L, 32 single-ended/16 differential inputs • sampling rates of single channel or multiple • channels is 110 K samples/sec • three different external trigger: post-trigger, pre-trigger, middle trigger • 16 digital input /16 digital output channels • 1002L : programmable low gain:1, 2, 4, 8. • 1002H: programmable high gain:1, 10, 100, 1000. • internal /external triggering.

  25. Commercial Capture Cards ADC card PC-1602 Price: $1286 • PCI bus • 16-bit 200KHz A/D converter  • 32 single-ended or 16 differential inputs 8K word FIFO buffer • the sampling rates of single channel or multiple  channels is: 200 k samples/sec • three different external trigger: post-trigger, pre-trigger, middle trigger • 16 digital input /16 digital output channels • PCI-1602 provides programmable low gain: 0.5, 1, 2, 4, 8 • internal/external triggering • two12-bit independent programmable DAC • high-speed data transfer rate (2.7 M Words)

  26. Commercial Capture Cards Card ADC 1,5PCI-14 Price: $586 • ADC: resolution: 14 bit, conversion time: 2,5 ms • 32 single-ended channels or 16 differential channels • input resistance is more than 100 М Ohm • switchable input voltage ranges of the ADC: ± 10V, ± 5V, ± 2,5V, ± 1V, ± 0,5V, ± 0,25V, ± • 0,1V, ± 0,05V (for each channel) • buffer memory of FIFO type, 2048 Words • high stable quartz generator 50 MHz and a programmable frequency devisor (from 5 upto • 31) • provides a wide grid of sampling rates • 16 digital lines: 8 - input and 8 - output

  27. References : 1) ADC Systems for SDR Digital Front-End N. vun, A. B. Premkumar, Senior members, IEEE 2) High-Resolution Analog-to-Digital Converters toward Software-Defined-Radio Receivers Akira FUJIMAKI, Yoshinori NISHIDO, and Akito SEKIYA, Members 3) Catalogs of Capture Cards from signal company

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