Pipelined CPU Design: Optimizing Performance and Efficiency

1. Phase 1 – Lecture – 2/25/2013

2. 1 Background

3. 2 Background

4. 3 Design Process • Identify a problem and define solution requirements • Break problem into smaller pieces • Research all possible solutions • Design all pieces to solution • Prove functionality of each piece separately • Integrate all pieces into working unit

5. 4 Process

6. 5 Research • Determine components used for each individual stage of our Pipelined CPU • Transition components to be used with other team’s stages of our Pipelined CPU • What are Reg Files? • What is Pipelining?

7. 6 Pipelining Computer Organization and Design, 4th Ed, D. A. Patterson and J. L. Hennessey

8. 7 Pipelining Our CPU

9. 8 Our CPU

10. 9 Front End The United States Postal Service

11. 10 Research - Roles • Park Lamerton – Lead Engineer • Nik Marinov – Intra Team Relations • Taylor Foster – Team Worker • Kelle McCan – Wiki Specialist • Melissa Allee - Historian

12. 11 Research - Timeline

13. 12 Front end mimics a mailing service Front End • Collect the mail. • Fetch instruction from memory. • Sort the mail. • Decode instruction. • Distribute data to desired locations. • Process replies. • Write back to destination register.

14. 13 Instruction Fetch Collecting the Mail • PC tells MEMORY what instruction to fetch. • PC controlled by two multiplexers. • One instruction fetched at a time.

15. 14 Types of instructions on the MIPS processor Instruction Encoding R-TYPE SHAMT RT OPCODE RS RD FUNCT 32 26 21 16 11 6 0 I-TYPE IMMEDIATE (offset, int, bit sequence) RS OPCODE RT 32 26 21 16 0 J-TYPE JUMP ADDRESS OPCODE 32 26 0

16. 15 Sort the mail Instruction Decode • Distribute data to proper locations. • Sign or Zero extend immediate value. • Forward register data to execution. • Write back computed results into desired register.

17. 16 Sort the mail Register File Read Data • Registers contain previously written or default values. • Mux forwards data based on the 5-bit register address. • All logic operations are performed on the rising edge of clock.

18. 17 Process replies Register File Write Back • Decode write back address. • Wait for control bit. • Write data to destination register. • All logic operations are performed on the falling edge of clock.

19. 18 Execution The Executives

20. 19 The Team • Michael Bowman – Lead Engineer • Laly Vang – Wiki Specialist • Matt Goranson – Intra Team Relations • Darryle Parker – Intra Team Relations • Matthew Horton – Report Compiler • Austin O’Neil – Historian

21. 20 Phase 1 Schedule

22. 21 Exposition • Responsible for instruction execution and address calculation • Topics: • ALU • Branch/Jump

23. 22

24. 23 Branch Logic • Why? • What? • Where?

25. 24 Branch Logic • BEQ • BNE

26. 25 Branch Logic • Depends on 3 signals • Zero • BNE Control • BEQ Control • PC + 4 is the default case (No branching/jumping)

27. 26 Jump Register R-type • It can take you places… .org 0x1000000 here: lui $t0 0xdead ori $t0 $t0 0xbeef jr $t0 nop

28. 27 R-type Jump… and Link Register Hey! Listen! Go places… and remember where we were (sort of). .org 0x1000000 here: li $t0 joy jalr $ra $t0 nop done: j done joy: jr $ra

29. 28 Jump and Link Register • Logic Required • Jump control signal – allows a jump • Jump register control – allows a jump from register • New address (register value) – where we’re going • Link control signal – pass a linked address to a register • Resultants • New PC address – where we’re going • PC control signal – allows update of PC • Next instruction address (PC+4) for write back – the linked address

30. 29 Jump • Very much like Jump Register, only we’re jumping to an immediate • But we’re limited. Instructions are 32 bits with the most significant six bits being the operation code. • We’ve only got 26 bits to work with, but we can use up to 28. • First two bits 0 next 26 bits from the jump address field and upper four bits from the old PC value • Jump logic • Jump Immediate – allows an immediate jump to a new location • Value from register – the new address • Jump Control – to allow a jump

31. 30 Jump and Link • Similar to JALR but uses the same address scheme used in Jump • Saves address for future use • Jump logic • Jump Immediate – allows an immediate jump to a new location • Jump Register Control Signal – allows register value to be taken • Value from register – the new address • Link Control Signal – to pass a linked address to a register

32. 31 ALU • Main math unit

33. 32 Exposition: ALU • “Arithmetic and Logic Unit” • Performs arithmetic and logical operations. • Does any calculations necessary to execute an instruction

34. 33 5-bits: 4-bit encoding with extra Sub bit 12 Operations Encoding

35. 34 Adder/Subtractor ADD Result = Op1 + Op2 SUB Result = Op1 - Op2 = Op1 + (!Op2 + 1) = (Op1 +!Op2) + 1

36. 35 SLT/SLTU SLT Easy SLTU Similar, but a caveat

37. 36 Simple Logic

38. 37 Logical Shifts SLL SRL

39. 38 LUI

40. 39 MULLO/MULHI

41. 40 Controls Controlling your life, everyday.

42. 41 The Team • Kory Teague – Lead Engineer • Kyle Lawler – Wiki Specialist • Andres Vega – Intra Team Relations • Bryan Rogers – Team Worker • Michael Oltmanns - Historian

43. 42 Responsibilities • Manage the Control Path • All non-hazard control logic • Memory Stage • Writeback Stage

44. 43 Processor Design

45. 44 Control Signals

46. 45 Declared Signals

47. 46 Signal Definitions

48. X ≡ 0 on all signals except SE, where X ≡ 1 47 Research

49. 48 Control Unit Design

50. 49 ALUControl Unit Design