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This document explores the critical variability factors affecting front-end of line (FEOL) electrical components, including transistors, capacitors, and resistors. Key topics include threshold voltage variations, inter-fab variations, channel width variations, and the impact of spacer thickness. We also discuss techniques to manage across-chip line-width variations (ACLV) and the importance of device length and spatial positioning to maintain performance. Additionally, we analyze hot carrier effects and drain resistance modulation, along with other less understood variations like Negative Bias Temperature Instability (NBTI).
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Front-End-Of-Line Variability Considerations EE/MatE 167 David Wahlgren Parent EE/MAtE167
Introduction • FEOL variability affects the response of discrete electrical components. • transistors, capacitors, resistors • MOSFET • Poly gate length • Spacer widths • Gate oxide thickness • Device width and edge effects EE/MAtE167
Threshold Voltage EE/MAtE167
Inter fab variation • Spacer thickness • Simple method • Large spacers • Leads to larger overlap variations • LDD • Narrow spacers • spacer then LDD implant • 20% spacer then S/D implant • Channel length can vary by 10% on die for even a mature process EE/MAtE167
Across the Chip Line-width Variation (ACLV) • How the line with varies on the die. • To combat ACLV have device gates: • have the same physical dimensions • oriented in the same direction • close together • have same nearest neighbor distances • are placed in area with similar pattern density. EE/MAtE167
NMOS to PMOS Length Tracking • The ratios of NMOS and PMOS driving capability vary. • Some styles are very dependant on this. • Even though the gates are etched at the same time, differences in spacers for pmos and nmos can affect LEFF • Some times they do not track • leff of nmos gets larger while pmos gets smaller across die. • Keep device length the same. • Keep everything close together. EE/MAtE167
Channel Width Variations • For narrow channel widths the threshold voltage can change. • Unlike SCE the effect can be directly proportional to width or inversely proportional with width fro fabrication house to fabrication house. EE/MAtE167
VT Variations • Everything varies but Planck’s constant and Boltzman’s constant • Threshold voltage • Gate oxide thickness • Doping in the channel • Channel Length • Fixed oxide charge • Mobile charge EE/MAtE167
Hot Carrier Effects • Degrades devices over the lifetime depending on how much they are used. • Since all gates are not used the same amount except for clock trees there will be a ID/VT variation that will creep in over time. • NMOS VT goes up ID goes down. • PMOS VT goes down ID goes up. EE/MAtE167
Type of HCE • Conducting • In “pinch off” Inversion region does not reach depletion region and carriers are inject with a high electric field. This gives them a high energy or temperature and it causes crystal damage. • Worse when VDD/2 • Slow slew rates or fast switching degrades FET even faster. • Energetic carriers get trapped in the gate oxide. EE/MAtE167
Drain Resistance Modulation • If spacer is too short dopant can get trapped in spacer thus lowering drain conductance. • If too large there is too much overlap capacitance and the speed goes down. EE/MAtE167
Other Variations • Negative Bias Temperature Instability • Inter fab variation • not well understood • aging • Body effect • Threshold voltage can vary if source is not tied to ground. EE/MAtE167
