Auto-adaptive reconfigurable architecture for scalable multimedia applications

1. Auto-adaptive reconfigurable architecture for scalable multimedia applications PhDstudent: Xun zhang Director of project :Professor Serge WEBER Co-director of project : Hassan RABAH Université Nancy Laboratoire d’Instrumentation d’Electronique de Nancy (LIEN)

2. Outline • Introduction • The need of auto-adaptation • Platform et auto-adaptation • Solution reconfigurable hardware • Implementation challenge • Exploration of auto-adaptive reconfigurable architecture • Multi-level adaptation • Multi-level reconfigurable Architecture • Test & analyze • Motivation of experiment • Application described • Result analyse • Summary and outlook

3. The need of auto-adaptation ? Introduction Auto-adaptation is not only a solution to adapt the change of application , but also a solution to make the system optimize itself to adapt the best performance in run-time, when a reconfiguration event is being happen. auto-adaptation in multimedia application ? • Auto-adaptation on thechoose of different filter • different filter in the different frequency domain (DCT, DWT) • Auto-adaptation on the choose of the scale of algorithme kernels(DCT, DWT,FIR,etc) • different size of resource ( size of image, level of decomposition or reconstruction) • different energy mode to adapt the energy computation

4. Hardware Solution Input 1 Input 2 Input 1 Input 2 ASIC 1 ASIC 2 ASIC 3 flexible Solution Input 2 Input 1 Input 2 Input 1 Introduction -- Auto-adaptation et Plateforme Software Solution Instructions resources memories Reconfiguration Computing Banc de registres REG REG REG Microprocessors REG ASICs ALU Solution performante Highest flexibility Performance? Highest performance Lowest flexibility High flexibility High performance µP output • GPPs can execute any software, but performance can be slow • ASICs can execute only one application, but quickly • Reconfigurable computing seeks to bridge this gap • Reconfiguration allows same hardware to execute multiple applications • Executing application in hardware leads to higher performance than in software

5. Introduction application 2 application 1 architecture 1 Architecture 2 configuration 1 configuration 2 configuration Physic Reconfigurable architecture --reconfigurable hardware Solution Configurable elements of computations and memories Configurable network of connexions reconfiguration

6. Implementation Challenge --FPGA Perform Processing Both in Space and Time Space --Memory size/Gate Number/Silicon area Refers to Physical Implementation of different functionality in vast hardware resources (parallel processing) Time --the reconfiguration Latency FPGAbe reconfigured at various steps of the application algorithm to instantiate different architectures at different run times(dynamic) Increasing of reconfiguration frequency Increasing of the size of reconfigurable module • Effective Organization solution for those reconfiguration resource on chip!! • Auto-adaption the status of platform in real-time for optimization of the reconfiguration process Requirement of client Complexity of application  Unified architecture

7. Exploration of auto-adaptive reconfigurable architecture • Multi-level adaptation • Multi-level reconfigurable Architecture

8. Specific processing tasks common processing tasks Two-levels adaptation sub tasks • Application adaptation --the switching between different applications The process of configuration from one application to another , which is happen to one or group of application task . • task adaptation • --the switching different versions of a task of an application  View of architecture

9. Multi-levels reconfiguration structure IP_2 memory IP • Global reconfiguration level • Reusable and fixed component (Ips) • (Reconfigurable Processing module –RPM) • Reconfigurable interconnection • Partial reconfiguration processor IP_1 RC2 C1 C2 RC1 C3 It is possible to remove or replace totally one RPM and the communication between elements on chip in order to meet a particular need. • Local reconfiguration level the modification is happened into RPM, one part of RPM is reconfigured for adapting the Configuration need.

10. Auto-adaptive reconfigurable architecture • Multi-Reconfigurable Pressing Module (RPM) • Register file • Reconfigurable Data path • On chip memory • RPM interface • Reconfigurable Interface • Inter-RPM • Intra-RPM • Reconfiguration manager • answer the reconfiguration request from exernal • Identify reconfiguration level • active the reconfiguration process

11. Exploration flow Spécification DAG des fonctions de l’application F6 Configuration resource F5 F4 ESTIMATION of application F3 F2 Configuration resourcelibrary F1 Event Library architecturale Organisation When? Modélisée(DBRC) Reconfiguration event activation ID of those modules n°1 Which modules are necessary? Architecture chosin g On-line Status of platform Estimation of architecture Configuration flow

12. Test and analyses • objectives of experiment • Application described • Result analyse

13. Application described t1 t2 RGB2YCbCr t3 DWT Quantize Configuration Event Definition t4 EBCOT Wavelet filter (5,3) t5 Event library JPEG2000

14. Discrete Wavelet Transform(DWT) Exemple of two levels copression and reconstruction DWT Experiment step: • Define two different DWT filter mode • Perform 2 level DWT decomposition on FPGA • Change the chosen DWT filter in run-time through partial reconfiguration

15. Configuration resourcelibrary Application described With an unique ID (5,3) • Discrete Wavelet Tranform (DWT) update (9,7)’ communication Communication’ Event library Filter(9,7) Filter(5,3) Implementation phase

16. Target Technique Experiment : Xilinx Virtex4 Partial reconfiguration platform More than one partial reconfiguration module (RPM) within a CLB colum Configuration frame is 16CLBs High ICAP (100 MHz) distributed LUT RAM scan be placed above or below a partial reconfiguration module Picture Source of Xilinx  Implementation result

17. Experimental results Place in tool PlanAhead View in FPGA Editor

18. Experimental results(Continue) • The reconfiguration time filter(5,3): part2+part3 filter(9,7): Part1+part3+part4 Tconfig = TICAP + TBRAM Ticap = L/r L: the length of the partial reconfiguration file r: the transfer rate with configuration clock frequency

19. Discussion • Summary • Definition of auto-adaptation from the view of architecture • Based-cluster models consist hierarchic reconfiguration modules • Multi-levels adaptation represents practically the complex application system • Experimentalresult to represent the implementation of this architecture

20. Thanks for your attention • Any question Nancy Universityhttp://www.uhp-nancy.fr Laboratoire d’Instrumentation Electronique de Nany (LIEN) http://www.lien.uhp-nancy.fr