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Chapter 6 Multi-channel Buffered Serial Port (McBSP)

Chapter 6 Multi-channel Buffered Serial Port (McBSP). Objectives. Definition of Terms: Bit, word or channel, frame and phase. Understand basic serial port operation. Understand clock generation. Pin polarity. Serial port interrupts. Describe multi-channel operation.

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Chapter 6 Multi-channel Buffered Serial Port (McBSP)

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  1. Chapter 6 Multi-channel Buffered Serial Port (McBSP)

  2. Objectives • Definition of Terms: • Bit, word or channel, frame and phase. • Understand basic serial port operation. • Understand clock generation. • Pin polarity. • Serial port interrupts. • Describe multi-channel operation. • Programming the serial port.

  3. Basic Definitions: Bits, Words ? CLK FS a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 Word Bit Serial Port 7 5 SP Ctrl (SPCR) RWDLEN1 Rcv Ctrl (RCR) Xmt Ctrl (XCR) 7 5 Rate (SRGR) XWDLEN1 Pin Ctrl (PCR) Data Data • “Bit” - one data bit per SP clock period. • “Word” or “channel” contains #bits specified byWDLEN1 (8, 12, 16, 20, 24, 32).

  4. Basic Definitions: Frame? FS w6 w7 w0 w1 w2 w3 w4 w5 w6 w7 Data Frame Word 8 14 RFRLEN1 8 14 XFRLEN1 • “Frame” - contains one or multiple words • FRLEN1 specifies #words per frame (1-128) Serial Port 7 5 SP Ctrl (SPCR) RWDLEN1 Rcv Ctrl (RCR) Xmt Ctrl (XCR) 7 5 Rate (SRGR) XWDLEN1 Pin Ctrl (PCR)

  5. Basic Definitions - Phase FS 1 2 3 A B Phase 1 Phase 2 Frame Phase 2 Phase 1 31 30 24 23 21 PHASE RFRLEN2 RWDLEN2 31 30 24 23 21 PHASE XFRLEN2 XWDLEN2 Data • Note: dual-phase used in Audio Codec97 (AC97) Std • Each FRAME can contain only 1 or 2 PHASES (PHASE). • Each PHASE can contain different #bits (WDLEN1/2) and #words (FRLEN1/2) . Serial Port 8 7 5 14 SP Ctrl (SPCR) RFRLEN1 RWDLEN1 Rcv Ctrl (RCR) Xmt Ctrl (XCR) 8 7 5 14 Rate (SRGR) XFRLEN1 XWDLEN1 Pin Ctrl (PCR)

  6. Basic Definitions - Phase 8 16 Phase 2 Phase 1 1 0001 010 0010 000 1 0001 010 0010 000 FS Data 1 2 3 A B Phase 1 Phase 2 Frame • Each FRAME can contain 1 or 2 PHASES (PHASE). • Each PHASE can contain different #bits (WDLEN1/2) and #words (FRLEN1/2) . • From above example some of the bit fields of RCR and XCR can be initialised as shown below. Serial Port 8 7 5 31 30 24 23 21 14 SP Ctrl (SPCR) PHASE RFRLEN2 RWDLEN2 RFRLEN1 RWDLEN1 Rcv Ctrl (RCR) Xmt Ctrl (XCR) 8 7 5 31 30 24 23 21 14 Rate (SRGR) PHASE XFRLEN2 XWDLEN2 XFRLEN1 XWDLEN1 Pin Ctrl (PCR)

  7. Definitions - Review CLK b1 b2 8 7 5 31 30 24 23 21 14 RFRLEN2 RWDLEN2 RFRLEN1 RWDLEN1 PHASE 8 7 5 31 30 24 23 21 14 PHASE XFRLEN2 XWDLEN2 XFRLEN1 XWDLEN1 Word 1 Word 2 Word 3 FS Phase 1 Phase 2 Phase 1 Phase 2 Frame 1 Frame 2 Serial Port SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR)

  8. Objectives • Definition of Terms: • Bit, word or channel, frame and phase. • Understand basic serial port operation. • Understand clock generation. • Pin polarity. • Serial port interrupts. • Describe multi-channel operation. • Programming the serial port.

  9. McBSP Block Diagram (Read) CPU RINT REVT RSR R B R D R R DR Peripheral Bus 32 CLKR DMA FSR

  10. McBSP Block Diagram (Write) CPU RINT REVT XEVT XINT DR Peripheral Bus 32 CLKR CLKX DMA FSR FSX RSR R B R D R R XSR D X R DX

  11. McBSP Block Diagram (Configuration) Periph Bus DR CLKR Serial PortControl Logic Multi-Channel BufferedSerial Port (McBSP) CPU DRR RSR RBR DXR DX XSR CLKX DMA RCR ? FSR SPCR XCR ? FSX Peripheral Bus

  12. Serial Port - Basic Operation CPU Periph Bus DR DX CLKR Serial PortControl Logic CLKX DMA RCR SRGR FSR SPCR FSX XCR PCR Peripheral Bus Multi-Channel BufferedSerial Port (McBSP) DRR RSR RBR DXR XSR “TRANSMIT” “RECEIVE”

  13. McBSP Registers (1) RSR Receive Shift Reg RBR Receive Buffer Reg DRR Data Receive Reg Receive XSR Transmit Shift Reg DXR Data Transmit Reg Transmit SPCR Serial Port Control Reg RCR Receive Control Reg XCR Transmit Control Reg Control

  14. Objectives • Definition of Terms: • Bit, word or channel, frame and phase. • Understand basic serial port operation. • Understand clock generation. • Pin polarity. • Serial port interrupts. • Describe multi-channel operation. • Programming the serial port.

  15. Configure CLK and FS as inputs or outputs Serial PortControl Logic Multi-Channel BufferedSerial Port (McBSP) CLKR CLKX RCR SRGR FSR SPCR FSX XCR PCR • FSR, FSX, CLKR and CLKX can be configured either as inputs or outputs, depending on the application.

  16. Configure CLK and FS as inputs or outputs Serial PortControl Logic Serial Port SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Multi-Channel BufferedSerial Port (McBSP) CLKR CLKX RCR SRGR FSR SPCR FSX XCR PCR CLK/FS Mode 0: Input 1: Output 10 8 11 9 FSXM FSRM CLKXM CLKRM

  17. Generating CLK and FS as output Serial Port SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) 10 8 11 9 Rate (SRGR) FSXM FSRM CLKXM CLKRM Pin Ctrl (PCR) ‘C6000 FSR FSX CLKR CLKX CLK/FS Mode 0: Input 1: Output

  18. Generating the CLK as output Sample Rate Generator (SRGR) CLKOUT1 FSR FSX CLKS CLKGDV CLKR CLKX CLKG 29 7 0 CLKSM CLKGDV ‘C6000 CLKSM • CLKSM - selects clock src (CLKOUT1 or CLKS) • CLKGDV - divide down (1-255) • CLKG = (input clock) / (1 + CLKGDV) • Max transfer rate = CLKG = 150 MHz/2 = 75 Mb/s Serial Port SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR)

  19. Generating the FS as output Sample Rate Generator (SRGR) CLKOUT1 FSR FSX FPER FSG CLKS CLKGDV CLKR CLKX CLKSM ‘C6000 CLKG • FSGM: 0 - FS gen’d on every DXR XSR copy 1 - FS gen’d by FSG • FPER: frame sync period (12 bits) Serial Port • FWID: frame sync pulse width (8 bits) SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) 29 28 27 16 15 8 7 0 Rate (SRGR) CLKSM FSGM FPER FWID CLKGDV Pin Ctrl (PCR)

  20. McBSP Registers (2) RSR Receive Shift Reg RBR Receive Buffer Reg DRR Data Receive Reg Receive XSR Transmit Shift Reg DXR Data Transmit Reg Transmit SPCR Serial Port Control Reg RCR Receive Control Reg XCR Transmit Control Reg SRGR Sample Rate Generator Control

  21. Objectives • Definition of Terms: • Bit, word or channel, frame and phase. • Understand basic serial port operation. • Understand clock generation. • Pin polarity. • Serial port interrupts. • Describe multi-channel operation. • Programming the serial port.

  22. Configure CLK and FS pin polarity Serial PortControl Logic Serial Port SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Multi-Channel BufferedSerial Port (McBSP) CLKR CLKX RCR SRGR FSR SPCR FSX XCR PCR CLK/FS Polarity 0: Falling edge 1: Rising Edge 2 0 3 1 FSXP FSRP CLKXP CLKRP

  23. Objectives • Definition of Terms: • Bit, word or channel, frame and phase. • Understand basic serial port operation. • Understand clock generation. • Pin polarity. • Serial port status and interrupts. • Describe multi-channel operation. • Programming the serial port.

  24. RRDY/XRDY Status and Interrupts RBR DRR EDMA XSR DXR Sync • RRDY/XRDY displays the “status” of the read and transmit ports: • 0: not ready. • 1: ready to read/write. CPU RINT XINT RRDY=1 “Ready to Read” • There are 3 methods for detecting if data is ready: • Poll SPCR bits via s/w. • Config CPU ints (RINT/XINT). • Program DMA sync events. XRDY=1 “Ready to Write” Serial Port SP Ctrl (SPCR) 17 1 Rcv Ctrl (RCR) XRDY RRDY Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR)

  25. Other sources of Interrupts (R/XINT) “Trigger Event” RRDY (RINTM=00b) End of Block (RCV) (RINTM=01) New FSR (frame begin) (RINTM=10b) Receive Sync Error (RINTM=11b) XRDY (XINTM=00b) End of Block (XMT) (XINTM=01b) New FSX (frame begin) (XINTM=10b) Transmit Sync Error (XINTM=11b) CPU RINT XINT Serial Port SP Ctrl (SPCR) 21 20 17 4 1 5 Rcv Ctrl (RCR) XINTM XRDY RINTM RRDY Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR)

  26. Objectives • Definition of Terms: • Bit, word or channel, frame and phase. • Understand basic serial port operation. • Understand clock generation. • Pin polarity. • Serial port status and interrupts. • Describe multi-channel operation. • Programming the serial port.

  27. Multi-Channel operation . . . . . . DR/X Ch0 Ch1 Ch31 Ch0 Ch1 Ch31 FSR/X How do you enable/disable each channel?

  28. Multi-Channel operation Multi-Channel Master (MCR) Rcv En (RCER) Xmt En (XCER) . . . . . . DR/X Ch0 Ch1 Ch31 Ch0 Ch1 Ch31 FSR/X • You can enable or disable any channel. RCER/XCER Enable Bits Enable [1] Disable [0] 31 0 0 … 1 1 1 0 RCER 31 0 XCER

  29. Multi-channel example Frame 2 Frame 1 4 3 2 1 4 3 2 1 Frame 3 4 3 2 1 Memory 1 3 1 3 . . . 1 3 F r a m e r M c B S P • Allows multiple channels (words) to be independently selected for transmit and receive.

  30. Multi-channel and EDMA combination used for channel sorting F r a m e r Frame 3 Frame 2 Frame 1 4 3 2 1 4 3 2 1 4 3 2 1 M c B S P E D M A Memory 1 1 1 . . . 3 3 3 • EDMA’s can sort each channel into separate buffers!

  31. EDMA Channel Sorting F r a m e r Frame 3 Frame 2 Frame 1 4 3 2 1 4 3 2 1 4 3 2 1 M c B S P E D M A Memory 1 1 1 . . . 3 3 3 • EDMA’s flexible (indexed) addressing allows it to sort each channel into separate buffers! • How do you select channels? ...

  32. Enable/Disable Channels 31 0 Multi-Channel … 1 0 1 0 RCER Master (MCR) Rcv En (RCER) 31 0 Xmt En (XCER) XCER • RCER / XCER registers allow you to enable or disable only 32-channels. • So how does the C6000 supports 128 channels?

  33. 128 Channels! Channels 0-15 16-31 32-47 48-63 64-79 80-95 96-111 112-127 31 16 15 0 Multi-Channel B15-0 A15-0 RCER Master (MCR) Rcv En (RCER) 31 16 15 0 Xmt En (XCER) B15-0 A15-0 XCER A B Interrupt To be able to support 128 channels the following applies: • Channels are broken into BLOCK’s (16 contiguous channels). • Up to 32 channels (2 BLOCK’s) can be enabled at any one time. • Channels are enabled via _CER registers and _BLK bits in MCR. • After 16 channels, McBSP issues END_OF_BLOCK interrupt. • CPU ISR re-programs RCER (or XCER) for channels 32-47 and so on.

  34. McBSP Registers (3) RSR Receive Shift Reg RBR Receive Buffer Reg DRR Data Receive Reg Receive XSR Transmit Shift Reg DXR Data Transmit Reg Transmit SPCR Serial Port Control Reg RCR Receive Control Reg XCR Transmit Control Reg SRGR Sample Rate Generator PCR Pin Control Reg Control MCR Multi-Channel Ctrl Reg RCER Rcv Channel Enable Reg XCER Xmit Channel Enable Reg

  35. Objectives • Definition of Terms: • Bit, word or channel, frame and phase. • Understand basic serial port operation. • Understand clock generation. • Pin polarity. • Serial port status and interrupts. • Describe multi-channel operation. • Programming the serial port.

  36. Programming the Serial Port • There are three methods available for programming the serial port: 1. Writing directly to the serial port registers. 2. Using the Chip Support Library (CSL). 3. Graphically using the DSP/BIOS GUI configuration tool.

  37. Programming the Serial Port - Direct (A) Writing directly to the serial port registers: • Although this method is straight forward, it relies on a good understanding of the serial port functionality. • This method can be tedious and is prone to errors. #include <c6211dsk.h> void mcbsp0_init() { *(unsigned volatile int *)McBSP0_SPCR = 0; *(unsigned volatile int *)McBSP0_PCR = 0; *(unsigned volatile int *)McBSP0_RCR = 0x10040; *(unsigned volatile int *)McBSP0_XCR = 0x10040; *(unsigned volatile int *)McBSP0_DXR = 0; *(unsigned volatile int *)McBSP0_SPCR = 0x12001; }

  38. Programming the Serial Port - CSL (1/4) (B) Using the Chip Support Library: • The CSL provides a C language interface for configuring and controlling the on-chip peripherals, in this case the Serial Ports. • The library is modular with each module corresponding to a specific peripheral. This has the advantage of reducing the code size. • Some modules rely on other modules also being included, for example the IRQ module is required when using the EDMA module.

  39. Programming the Serial Port - CSL (1/4) MCBSP_Handle hMcbsp; hMcbsp = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET); • CSL programming procedure: (1) Create handles for the serial ports: (2) Open the serial port:

  40. Programming the Serial Port - CSL (2/4) • CSL programming procedure: (3) Create a configuration structure for serial port: • \Links\McBSP_Config_Struct.pdf

  41. Programming the Serial Port - CSL (3/4) MCBSP_close(hMcbsp); • CSL programming procedure (cont): (4) Configure the serial port: (5) Close the Serial Port after use: MCBSP_config(hMcbsp,&ConfigLoopback);

  42. Programming the Serial Port - CSL (4/4) Practical example on DSP Code 6711 • Project name: mcbsp_dynamiccfg.pjt • Location: \Code\Chapter 06 - McBSP\Dynamic_CSL_Config\

  43. Programming the Serial Port using the DSP/BIOS GUI (C) DSP/BIOS GUI Interface: • With this method the configuration structure is created graphically and the setup code is generated automatically.

  44. Programming the Serial Port using the DSP/BIOS GUI • Procedure: (1) Create a configuration using the MCBSP Configuration manager (eg. mcbspCfg0).

  45. Programming the Serial Port using the DSP/BIOS GUI • Procedure: (2) Right click on mcbspCfg0 and select “Properties”, see figures below, and then select “Advanced” and fill all parameters as shown below:

  46. Programming the Serial Port using the DSP/BIOS GUI • Procedure: (3) Select the serial port you would like to use from the MCBSP Resource manager (eg. Mcbsp_Port1). Right click and select properties. Select the mcbspCfg0 configuration just created.

  47. Programming the Serial Port using the DSP/BIOS GUI • Procedure: (4) A file is then generated that contains the configuration code. The file generated for this example is shown on the next slide.

  48. Programming the Serial Port using the DSP/BIOS GUI /* Do *not* directly modify this file. It was */ /* generated by the Configuration Tool; any */ /* changes risk being overwritten. */ /* INPUT mcbsp1.cdb */ /* Include Header File */ #include "mcbsp1cfg.h" /* Config Structures */ MCBSP_Config mcbspCfg0 = { 0x00008000, /* Serial Port Control Reg. (SPCR) */ 0x000000A0, /* Receiver Control Reg. (RCR) */ 0x000000A0, /* Transmitter Control Reg. (XCR) */ 0x203F1F0F, /* Sample-Rate Generator Reg. (SRGR) */ 0x00000000, /* Multichannel Control Reg. (MCR) */ 0x00000000, /* Receiver Channel Enable(RCER) */ 0x00000000, /* Transmitter Channel Enable(XCER) */ 0x00000A00 /* Pin Control Reg. (PCR) */ }; /* Handles */ MCBSP_Handle hMcbsp1; /* * ======== CSL_cfgInit() ======== */ void CSL_cfgInit() { hMcbsp1 = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET); MCBSP_config(hMcbsp1, &mcbspCfg0); }

  49. Programming the Serial Port using the DSP/BIOS GUI /* Do *not* directly modify this file. It was */ /* Config Structures */ MCBSP_Config mcbspCfg0 = { 0x00008000, /* Serial Port Control Reg. (SPCR) */ 0x000000A0, /* Receiver Control Reg. (RCR) */ 0x000000A0, /* Transmitter Control Reg. (XCR) */ 0x203F1F0F, /* Sample-Rate Generator Reg. (SRGR) */ 0x00000000, /* Multichannel Control Reg. (MCR) */ 0x00000000, /* Receiver Channel Enable(RCER) */ 0x00000000, /* Transmitter Channel Enable(XCER) */ 0x00000A00 /* Pin Control Reg. (PCR) */ }; Few remarks: (1) Notice that values in the code generated are the same as the values inserted using the GUI interface.

  50. Programming the Serial Port using the DSP/BIOS GUI Few remarks: (2) Do not forget to close the serial port after use. (3) To visualise the output of the logprintf () function make sure that the Message Log window is open (DSP/BIOS > Message Log).

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