1 / 38

A Monte Carlo Approach for Testability Analysis

A Monte Carlo Approach for Testability Analysis. Speaker: Chuang-Chi Chiou Advisor: Chun-Yao Wang 2007.01.29. Outline. Introduction Previous Work Background Monte Carlo Approach for testability analysis Experiment Results Conclusion Future Work. Outline. Introduction Previous Work

willow-terry
Télécharger la présentation

A Monte Carlo Approach for Testability Analysis

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. A Monte Carlo Approach for Testability Analysis Speaker: Chuang-Chi Chiou Advisor: Chun-Yao Wang 2007.01.29 1

  2. Outline • Introduction • Previous Work • Background • Monte Carlo Approach for testability analysis • Experiment Results • Conclusion • Future Work 2

  3. Outline • Introduction • Previous Work • Background • Monte Carlo Approach for testability analysis • Experiment Results • Conclusion • Future Work 3

  4. Single Stuck-At Fault Only one line is faulty Fault line permanently set to 1 or 0 Fault can be an input or output of a gate One of the gate input terminal was mistakenly connected to ground Fault: B stuck at 0 Signal B is always be 0 Fault Model G1 A B 4

  5. Testability Analysis • Controllability • The difficulty of setting a particular logic signal to 0 or 1 ( 0’s controllability or 1’ controllability ) • Observability • The difficulty of observing the state of a logic signal • Fault detection probability • Stuck-at-1 fault testability • Stuck-at-0 fault testability • The difficulty of observing the state of a logic signal to be 0 or 1 5

  6. Motivation • Give a warning to designer which nodes are hard-to-test • Redesign • Add test circuits such as test point insertion • Provide guidance for ATPG • Avoid hard-to-control point • Provide estimation of fault coverage and test vector set length 6

  7. Outline • Introduction • Previous Work • Background • Monte Carlo Approach for testability analysis • Experiment Results • Conclusion • Future Work 7

  8. Previous Work (1/2) • SCOAP • First elegant formulation • Use integer to represent difficulty for testing a wire • Results are not easy to use • Parker and McCluskey • Definition of probabilistic controllability • Symbolic expression • Expression grows exponentially • COP • Probability based • Correlation is not taken into account • Very fast but low accuracy 8

  9. Previous Work (2/2) • PREDICT • First exact probabilistic measures • Use supergate concept • High accuracy but exponential computation • TAIR • Use ATPG to revise the result of COP • Much accurate than COP • Still has 20%–30% inaccuracy in general circuits • Inaccuracy is augmented by the correlation 9

  10. Outline • Introduction • Previous Work • Background • Monte Carlo Approach for testability analysis • Experiment Results • Conclusion • Future Work 10

  11. Monte Carlo Approach • Random number generator • Sampling rule • Scoring • Accumulate into overall scores for the quantities • Error estimation • Estimation of the statistical error as a function of the number of trials 11

  12. Example for MC approach • Estimate π, “hit and miss” concept • Generate random number between 0 and 1 • Sampling rule • Sample interval 1000 points • Scoring • Accumulate sample data • Error estimation • Confidence interval • Define stop condition y 1 x 1 0 12

  13. Outline • Introduction • Previous Work • Background • Monte Carlo Approach for testability analysis • Experiment Results • Conclusion • Future Work 13

  14. Problem Description • Given a circuit only consists of AND, OR and INV gates • Calculate controllability, observability and s-a-0, s-a-1 fault detection probability for each node 14

  15. Random Pattern Architecture • RPG is a N-output circuit with parameterr • Generates N 2r-bit patterns 2rbits S R P G N M … … r 15

  16. Sampling Rule (1/5) • Controllability C0= 1/4 0110 C0= 2/4 a C1= 3/4 C0= 1/4 d C1= 2/4 0111 C1= 3/4 f C0= 2/4 0011 0011 0111 b C1= 2/4 0111 C0= 1/4 C1= 3/4 0011 e C0= 2/4 0101 c C1= 2/4 16

  17. Sampling Rule (2/5) • Observability O = 3/4 0110 a O = 1/4 d O = 4/4 0111 f 0011 0011 0111 b O = 2/4 O = 1/4 0111 O = 3/4 O = 1/4 0011 e 0101 c O = 1/4 17

  18. Sampling Rule (3/5) • Fault detection probability T1 = 0/4 T1 = 0/4 T0 = 3/4 0110 T1 = 1/4 a T0 = 1/4 d T0 = 3/4 0111 f 0011 0011 T1 = 0/4 0111 b T1 = 0/4 T1 = 0/4 T0 = 2/4 T0 = 3/4 0111 T0 = 1/4 T1 = 0/4 T0 = 1/4 0011 e T1 = 0/4 0101 c T0 = 1/4 18

  19. Sampling Rule (4/5) • Multiple path sensitization O = 3/4 0110 a O = 1/4 d O = 4/4 0111 f 1110 0011 0011 0111 b O = 2/4 1100 1100 1100 O = 3/4 0111 O = 3/4 O = 1/4 1101 O = 1/4 0011 0011 e 1100 0101 c O = 1/4 19

  20. Sampling Rule (5/5) • Multiple path sensitization O = 3/4 0110 a O = 1/4 d O = 4/4 0111 f 1110 0011 0011 0110 b O = 3/4 1100 1100 1010 O = 3/4 1110 O = 2/4 O = 1/4 1011 O = 2/4 0011 e 1100 1010 c O = 1/4 20

  21. Objective of Testability Analysis • Fast • Almost linear time complexity to circuit size • Provide high-accuracy approximate result • Neglect self-masking and multiple path sensitization 21

  22. Scoring (1/2) • Circuit: C6288 • Gates: 3540 • Frame : 1024 bits • Iteration: 100000 • Observe point : output • Normal Distribution 22

  23. Scoring (2/2) 23

  24. Error Estimation • Unknown mean unknown standard deviation • : sample mean, t*: value from t-distribution table at specified confidence level S : sample standard deviation n : number of iterations • We simulate the circuit until • ε: specified error 24

  25. Confidence Level • More confidence level more similar to Normal Distribution 25

  26. t-distribution Table • We choose 95% confidence level 5-degrees freedom 26

  27. Flow • Read circuit in BLIF format • Iteration • Random patterns for PIs • Evaluate • Back trace • Run several iterations to find check point • Highest standard deviation point • Check stopping criterion • Specified confidence level and error • Error estimation 27

  28. Start Specify r, c, ε,n i++ Generate 2r patterns Sample data no i > n ? yes Determine check point yes error <ε? no Average all sample data Generate 2r patterns Sample data Finish

  29. Outline • Introduction • Previous Work • Background • Monte Carlo Approach for testability analysis • Experiment Results • Conclusion • Future Work 29

  30. Experiment Results (1/5) • Frame: 8192 (213), Initial iterations: 10, C: 99.9%, ε: 0.005 30

  31. Experiment Results (2/5) • Frame: 8192 (213), Initial iterations: 10, C: 99.9%, ε: 0.005 31

  32. Experiment Results (3/5) • Frame: 8192 (213), Initial iterations: 10, C: 99.9%, ε: 0.005 32

  33. Experiment Results (4/5) • Frame: 8192 (213), Initial iterations: 10, C: 99.9%, ε: 0.005 33

  34. Experiment Results (5/5) 34

  35. Outline • Introduction • Previous Work • Background • Monte Carlo Approach for testability analysis • Experiment Results • Conclusion • Future Work 35

  36. Conclusion • Monte Carlo Approach is used for testability analysis • Parallel Pattern Simulation and Critical Path Tracing techniques is introduced as sampling rule • Our method is fast, high-accuracy and flexible 36

  37. Outline • Introduction • Previous Work • Background • Monte Carlo Approach for testability analysis • Experiment Results • Conclusion • Future Work 37

  38. Future Work • Finish ITC paper 38

More Related