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Exploration and application deployment on a SoC: efficient application

Exploration and application deployment on a SoC: efficient application. Paul Brelet TRT paul.brelet@thalesgroup.com. 24/11/2011. SoCKET Flow. System Requirements. System Properties. Global SoC Req. Metrics. Metrics. SoC Architecture. Traffic generator. HLS.

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Exploration and application deployment on a SoC: efficient application

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  1. Exploration and application deployment on a SoC: efficient application Paul Brelet TRT paul.brelet@thalesgroup.com 24/11/2011

  2. SoCKET Flow System Requirements System Properties Global SoC Req. Metrics Metrics SoC Architecture Traffic generator HLS Requirements traceability Hardware properties Software properties Platform Assembly Headers generation IP-XactSoC C/C++/ASM TLMLT Software Functionality Functional validation Instruction Set Simulator TLMAT Fonctionnalité +timing Software SW Performance Validation RTL Software HLS Co-simulation/Co-emulation Silicon Software Execution

  3. Use case TRT – Description App. • Pedestrians detection • Algorithm of classification [Viola&Jones] • Two steps: • Off-line: training by an image database • On-line: detection by using the training results • Pedestrians tracking in an multi-camera environment • Use of the visual covering of the cameras in order to carry out the tracking • Utilization of descriptors of forms and/or colors in order to improve the tracking and to manage occlusions Workshop - November 2011

  4. Thales use case – App. Description • Schematic view of the pedestrian detection Workshop - November 2011

  5. Thales use Case – Architecture Host Architecture details Workshop - November 2011

  6. Thales use Case – Architecture Accelerator details (Engine) Workshop - November 2011

  7. Thales use Case – Flow • Host Definition: • IP-XACT requirements • SystemC/TLM generation • VHDL generation • Architecture Model generation for SPEAR Workshop - November 2011

  8. Thales use Case – Flow • Exploration and Simulation: • Architecture SystemC Model generation • Architecture Model generation for SPEAR • Catch the application on SPEAR • C code exists for each SPEAR box (TE) • Test of various strategies of application deployment: • Exploration of the level of granularity • How calculations are paralleled and which divisions data can be apply to minimize the I/O and to reach the performances • The accelerators are simulated in SystemC from TE C codes Workshop - November 2011

  9. Phase 1: Architecture Exploration • Library: SystemC2.2 / TLM2.01 • Tools: - SPEAR DE, - Magillem: Packager, Platform Assembly, MRV Generator. • Validation: Transactional Level. • Links: - IPXACT_2_SPEAR Generator (XSLT Script). Workshop - November 2011

  10. Thales Flow: Exploration IPs Packager MDS IP-XACT library Template JET PLT Assembly MDS MRV Generator IPXACT 2 SPEAR SystemCSkeleton client Spear Model Spear Application Exploration/ Validation Spear TE IO API TE TE KO Workshop - November 2011 OK

  11. Phase 2: HW Design • Level: RTL. • Tools: - GAUT: Apply on accelerator engines. - Magillem: Packager, Platform Assembly, Generator Studio. - SPEAR DE: Mapping • Validation : Register Level. • Links : - Scripts « bash ». Workshop - November 2011

  12. Thales Flow: RTL Validation Generator Studio Generic client TE SystemCSkeleton client GAUT IP-XACT library Template JET VHDL Acc. client PLT Assembly MDS MRV Generator Netlister MDS Vhdl Application Spear FPGA HAL Validation

  13. SPEAR DE Tool • SPEAR Flow Workshop - November 2011

  14. MAGILLEM Tool • RTL Level: - Bus interface, components creation, link between components: ditto TLM. • VHDL code generation: - Using generics. - The code is readable by an individual. - Inter-connects are taken into account during the VHDL code generation. Workshop - November 2011

  15. GAUT Tool • The C code: - The C code must be very close to VHDL code. - Based on gcc4.3.0 for the “cdfgcompiler” • Comparison with commercial tools: - Roccc, ImpulseC. • Some troubles during VHDL code generation: - The generated code can be synthesizable but it does not work well in placement/routing. Workshop - November 2011

  16. Using graphic interface Workshop - November 2011

  17. Using Bash Script Workshop - November 2011

  18. VHDL code generation Workshop - November 2011

  19. DFG Visualization

  20. Comparison: VHDL code generation • Principe Minimum between two images 3X3 Convolution Integral Image • Results Workshop - November 2011

  21. Outlines • To propose the projections of the tools for synthesis: - GAUT is an academic alternative compared to industrial tools. - MAGILLEM makes it possible to re-use the IPs blocks. • To consolidate the Thales Design Flow. • To transfer the Thales Design flow to an operational level. Workshop - November 2011

  22. Conclusion • To re-use the IPs blocks: - Time-saver and productivity in the design of System on Chip. • Validity of new Architecture: - Allow to check the information processing applications on the desired architecture. Workshop - November 2011

  23. Questions? Workshop - November 2011

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