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Programming FPGA for LiCAS ADC: Continuous Data Readout and Modifications Overview

This document outlines the programming of the FPGA in the LiCAS ADC system for continuous data readout. It discusses the current status of the Field-Space Interleaving (FSI) implementation and modifications yet to complete. Key topics include sampling and manipulation of data through an External FIFO, the FFI operation over USB, and necessary internal control signal modifications. The report highlights obstacles in FFI operation, new registry entries for mode selection, and the importance of routing data effectively without external components. Future work includes simulation, diagnostics, and extending sampling rate settings.

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Programming FPGA for LiCAS ADC: Continuous Data Readout and Modifications Overview

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  1. Programming of FPGAin LiCAS ADC forContinuous Data Readout Jack Hickish

  2. Programming the FPGA • Current Situation – FSI • Modifications made • Still to do…

  3. Sampling / Manipulation of data External FIFO FFI Operation RAM FIFO Data Out over USB The Current Situation - FSI Data In

  4. FFI Operation Data In Choice of FFI Data Path - Preserves ‘Test Mode’ feature and existing sampling method and rate controls - Requires no components outside the FPGN, for ease of simulation - USB interface requires some sort of memory buffer to compensate for fluctuations in USB data transfer rate Sampling / Manipulation FIFO Data Out over USB

  5. Data Path Data needs to be rerouted bypassing external RAM and FIFO Sampling Data is only taken for a fixed number of clock cycles. Data is only output after sampling period is complete. Read/write enabling system incompatible with constant readout Internal Control Signals Obstacles to FFI Operation

  6. Modifications New registry entries added to control operation mode New entries: “FFI MODE” bit 1 for FFI operation 0 for FSI operation Data Bus and Control signals (including sampling controls) intercepted by new components, which redirect and alter signals based on the state of the FFI MODE bit. “STOP” bit halts FFI operation Data Path Sampling Internal Control Signals

  7. Sampling / Manipulation of data External FIFO Data In FFI Operation RAM FIFO Data Out over USB Modifications

  8. bit = 1 Data in direct from Sampling control FIFO bit = 0 Data in from RAM USB Output “data_path_selector” FFI mode bit Modifications

  9. Still to do… • Simulation • Output Data Rate • Clock Divider • Extension of existing sampling rate settings • Diagnostics • Notification (LED?) in case of failure in data path

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