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Efficient Hierarchical Indexing with Bloom Filters: A Scheme for IP Lookup

This paper presents a scheme for IP lookup using a Hierarchically Indexed Hash Table (HIHT) structured by Bloom Filters. The scheme covers insertion, query, modification, and deletion operations along with performance metrics and simulations for IP lookup. Detailed concepts include hashing functions, memory consumption, and time complexity analysis. The proposed scheme utilizes a dual Hierarchical Indexing Tree (HIT) design along with valid bit arrays and free address stacks for efficient data handling.

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Efficient Hierarchical Indexing with Bloom Filters: A Scheme for IP Lookup

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  1. A SPACE- AND TIME-EffiCIENT HASH TABLE HIERARCHICALLY INDEXED BY BLOOM FILTERS Author: Heeyeol Yu and Rabi Mahapatra Publisher/Conf.: Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on Speaker: Han-Jhen Guo Date: 2009.05.20

  2. OUTLINE • The Proposed Scheme • Concept • Insertion • Query • Modification • Deletion • Insertion • Performance • Simulation for IP Lookup • Time Complexity • Memory Consumption

  3. THE PROPOSED SCHEME- CONCEPT • Basic configuration of hierarchical indexing tree of 0- and 1-tree

  4. THE PROPOSED SCHEME- CONCEPT • Hierarchically Indexed Hash Table (HIHT) • Assumption • hash functions are perfectly random • n keys → s = log2(n) layers (SRAM modules) • at same level i, each BF use mi-bit vector and kihash functions • The BFs in the hierarchical indexing tree (HIT) used for indexes to a key table is hierarchically partitioned to make indexes

  5. THE PROPOSED SCHEME- INSERTION • (eg. insert key = 011, rule = E, addr(key) = 4) 1-3. set all k1m1-bit vectors with hi(key) in parallel (0 <= i <= k1-1) 1-1. base addr = 100 * m1 * k1 key table rule table

  6. THE PROPOSED SCHEME- INSERTION • (eg. insert key = 011, rule = E, addr(key) = 4) 2-3. set all k2 m2-bit vectors with hi(key) in parallel (0 <= i <= k2-1) 2-1. base addr = 100 * m2 * k2 key table rule table

  7. THE PROPOSED SCHEME- INSERTION • (eg. insert key = 011, rule = E, addr(key) = 4) 3-3. set all k3m3-bit vectors with hi(key) in parallel (0 <= i <= k3-1) 3-1. base addr = 100 * m3 * k3 key table rule table

  8. THE PROPOSED SCHEME- INSERTION • (eg. insert key = 011, rule = E, addr(key) = 4) key table rule table

  9. THE PROPOSED SCHEME- QUERY • No f-positive (eg. search key = 01101011) calculate hi(key) in parallel (0 <= i <= k1-1 ) count 1’s = k1→ hit; A = 1 key table rule table

  10. THE PROPOSED SCHEME- QUERY • No f-positive (eg. search key = 01101011) calculate hi(key) in parallel (0 <= i <= k2-1 ) count 1’s = k2→ hit; A = 10 key table rule table

  11. THE PROPOSED SCHEME- QUERY • No f-positive (eg. search key = 01101011) calculate hi(key) in parallel (0 <= i <= k3-1 ) count 1’s = k3→ hit; A = 100 key table rule table

  12. THE PROPOSED SCHEME- QUERY • No f-positive (eg. search key = 01101011) A = 100 key table key is matched rule table

  13. THE PROPOSED SCHEME- QUERY • No f-positive (eg. search key = 01101011) key table rule table fetch relative rule

  14. THE PROPOSED SCHEME- QUERY • F-positive (eg. search key = 01101011) key table rule table

  15. THE PROPOSED SCHEME- QUERY • No f-positive (eg. search key = 01101011) A = 010 A = 100 key table key is unmatched key is matched rule table

  16. THE PROPOSED SCHEME- QUERY • No f-positive (eg. search key = 01101011) key table rule table fetch relative rule

  17. THE PROPOSED SCHEME- MODIFICATION • Dual HITs • valid bit array (VBA) • on-chip; indicate whether the key exists in the key table • next • on-chip; indicate the address for inserting next new key • free address stack (FAS) • off-chip; store addresses of empty spaces

  18. THE PROPOSED SCHEME- DELETION • No f-positive (eg. delete key = 011) 100 100 VBA 0

  19. THE PROPOSED SCHEME- DELETION • F-positive (eg. delete key = 001) 001 001 VBA 0 f-positive is checkedby unmatched key f-positive is checked

  20. THE PROPOSED SCHEME- INSERTION • (eg. insert key = 101, r = G) 001 VBA 1 101 G

  21. Performance- Simulation for IP Lookup • Architecture

  22. PERFORMANCE- SIMULATION FOR IP LOOKUP • Related work - Prefix collapsing • (eg. collapse stride = 3)

  23. PERFORMANCE- TIME COMPLEXITY • Average access time to a table or a linked list as a function of SS rate

  24. PERFORMANCE- MEMORY COMSUMPTION • On-chip memory size with various hash schemes for 6 BGP tables in 40Gbps and 160Gbps routers

  25. Thanks for your listening!

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