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Advanced VHDL Module Development for MGTs with C++ Instantiation and BERT Implementation

Working on top-level VHDL module for MGTs and connected algorithms, using C++ for instantiation and mapping. Also focusing on BERT on AVAGO-MINIPOD mezzanine board following Wojciech's format algorithms for RX (SIPO) and TX (PISO).

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Advanced VHDL Module Development for MGTs with C++ Instantiation and BERT Implementation

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  1. Current MGT status Work on Top-Level-VHDL modulewithinstantiated MGTs andconnectedalgorithms C++ basedinstantiationandmappingof MGTs in development Currently also busywith BERT on AVAGO-MINIPOD mezzanineboardbased on Wojciechs format algorithms RX (SIPO) TX (PISO)

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