1 / 21

Design of High Temperature Bias Generator at Oklahoma State University

This presentation by Chris Hutchens covers the design of a high temperature bias generator, including key concepts like the transistor bias generator equation, various configurations for biasing devices, and the implications of temperature on bias performance. It discusses the use of different types of devices, such as low VT and high VT transistors, and features insight into the startup circuit's design and optimization. The presentation aims to enhance understanding of bias generation in high-temperature environments, focusing on practical solutions and engineering optimizations.

zarola
Télécharger la présentation

Design of High Temperature Bias Generator at Oklahoma State University

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Oklahoma State University HIGH TEMPERATURE BIAS GENERATOR DESIGN Presented by:Chris Hutchens

  2. Outline • Transistor • The Bias Generator Equation • VB1 and VB4 • VB3 and VB4 • Stacking Low VT and High VT devices • Stacking “zero” VT and Low VT devices • Start-up Circuit

  3. Background 1 plus a small number Square Root of 1 plus a small number Square Root of 1 divided by plus a small number Example Veff difference of two NMOS transistors; Equal ID and S=32 and S=45.

  4. Bias Generator optional Bias VB1 thur VB4 Stack Bias Startup

  5. SOI Square Law

  6. Squqre Law Bias Equation VB1 VB4 M1 M2

  7. Squqre Law Bias Equation Low Headroom

  8. Peregrine 0.5um SOS VB3 and VB2

  9. Peregrine 0.5um SOS VB3 and VB2

  10. Peregrine 0.5um SOS Constant Gain Bias

  11. Peregrine 0.5um SOS Constant Gain Bias

  12. Peregrine 0.5um SOS Constant gm bias

  13. Peregrine 0.5um SOS Constant gm bias

  14. Peregrine 0.5um SOS Startup Circuit 2 Possible Solutions

  15. Peregrine 0.5um SOS Startup Circuit

  16. Startup Circuit Improved Start up Ckt 3rd Leg provides VB3

  17. SOI Subthreshold

  18. SOI Moderate Inversion

  19. SOI PSRR - plus Long Channel Cascode Long Channel

  20. SOI Temperature Considerations

  21. SOI Decouping of V Biases Trim Pot Engineering

More Related