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Signals vs. Variables Workshop Fri/Sat Test bench creation Misc IP Cores Chipscope Pro

Signals vs. Variables Workshop Fri/Sat Test bench creation Misc IP Cores Chipscope Pro When Demos due. Signals vs. Variables. Simple Code. Testbench Code. signal sig_s1: std_logic_vector(3 downto 0) := "0000"; begin proc1: process(clk)

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Signals vs. Variables Workshop Fri/Sat Test bench creation Misc IP Cores Chipscope Pro

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  1. Signals vs. Variables Workshop Fri/Sat Test bench creation Misc IP Cores Chipscope Pro When Demos due

  2. Signals vs. Variables Simple Code Testbench Code signal sig_s1: std_logic_vector(3 downto 0) := "0000"; begin proc1: process(clk) variable var_s1: std_logic_vector(3 downto 0) := "0000"; begin if ((clk'event) and (clk = '1')) then var_s1 := var_s1 + "0001"; var_s1 := var_s1 + "0001"; var_s1 := var_s1 + "0001"; sig_s1 <= sig_s1 + "0001"; sig_s1 <= sig_s1 + "0001"; sig_s1 <= sig_s1 + "0001"; res1 <= var_s1; res2 <= sig_s1; end if; end process; clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process;

  3. Signals vs. Variables The waveforms Adding sigs, vars, radix, grouping/moving items, saving .do

  4. Generating testbenches Auto file generation file new source – VHDL testbench

  5. Basic VHDL Concepts • Interfaces -- i.e. ports • Behavior • Structure • Test Benches • Analysis, simulation • Synthesis

  6. Requirements RTL Model Simulate Synthesize Gate-levelModel Simulate Test Bench ASIC or FPGA Place & Route TimingModel Simulate Basic Design Methodology Intro to VHDL

  7. Use of VHDL in Synthesis • VHDL was initially developed as a language for SIMULATION • Recently being used as a language for hardware synthesis from logic synthesis companies • Synopsys Design Compiler, Ambit BuildGates, Mentor Graphics Autologic, .. • Synthesis tools take a VHDL design at behavioral or structural level and generate a logic netlist • Minimize number of gates, delay, power, etc.

  8. Synthesizable Subset of VHDL • There are a number of constructs that cannot be synthesized into hardware • File operations including textio • Assertion statements • There are some generally accepted ways of entering VHDL descriptions such that it correctly synthesizes the logic

  9. Predefined Packages • The predefined types in VHDL are stored in a library “std’ • Each design unit is automatically preceded by the following context clause library std, work; use std.standard.all; package standard is type boolean is (false, true); -- defined for operators =, <=, >=, .. type bit is (‘0’, ‘1’); -- defined for logic operations and, or, not… type character is (..); type integer is range IMPLEMENTATION_DEFINED; subtype natural is integer range 0 to integer’high; type bit_vector is array(natural range <>) of bit; … end package standard;

  10. Bit Vectors • Signals can be more than one bit (a vector) • Represent P address and data, function selection, etc. • Declaration is similar to single bit signals • Type is bit_vector or std_logic_vector • We also must specify vector index range and direction • big endian: (low to high) • little endian: (high downto low) Bit Vectors and Data Flow VHDL

  11. Vector Declarations port ( A, B: in std_logic_vector(7 downto 0); Z: out std_logic_vector(1 to 16) ); A and B: Z: 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note! The first bit and last bit index numbers define the number of bits in the vector (i.e. max - min + 1) Bit Vectors and Data Flow VHDL

  12. Vector Literals • Single bit binary literals are ‘0’ and ‘1’ • Vector binary literals are “0101”, “10_01” • literal values may have an underscore embedded to improve readability • For bit_vectors we can also specify values using octal, decimal, or hexadecimal. • O”1234” D”1999” X”ABCD” • NOTE: This doesn’t work for std_logic_vectors and the Xilinx tools (use function “To_std_logic_vector” to translate)

  13. Vector Logical Operations • Single bit logical operations also apply to vectors • Operands MUST be the same size (generally applies to all vector operations) • Assignment target must also have the same number of bits as the result • Operations are applied bitwise to operands to produce the vector result

  14. Vector Operations Given: Signal A, B, Z: std_logic_vector(7 downto 0); Then the following logical operation and assignment Z <= A and B; Is equivalent to:

  15. Vector Arithmetic Operations • Vector arithmetic operations are basically the same as vector logical operations • Operands MUST be the same size • Assignment target must also have the same number of bits as the result • Operations are applied bitwise to operands to produce the vector result • The only difference is the carry or borrow • Carry in/out must be specially handled • Result can be 1 bit larger than operands (CO)

  16. IP Cores What is a core? Xilinx Cores OpenCores.org

  17. IP Cores For example I am using Tutorial 8 from here. Unfortunately the Adder/Subtractor is no longer in 10.1 so I am using the counter http://www.fpgamac.com/html/spartan3e_tutorials.html

  18. Chipscope Pro

  19. Demos of Tea Kettle with Chipscope Pro Friday 10 Oct 9am or Friday 10 Oct 4pm or Saturday 11 Oct 9am At the FMAC 2350 Alamo Avenue SE Suite 100

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