101-1 Under-Graduate Project Techniques in VLSI design

1. 101-1 Under-Graduate ProjectTechniques in VLSI design Speaker:Yu-Min Lin Advisor: Prof. An-Yeu Wu Date: 2012/10/23 Some slides come from Prof. Chien’s course — DSP in VLSI Design

2. Outline • Techniques in VLSI design • Iteration Bound • Pipelining & Parallel • Retiming • Unfolding / Folding

3. Critical Path • The path with the longest computation time among all paths that contain zero delays

4. Loop Bound • Loop — A directed path that begins and ends at the same node • Loop Bound — The lower bound on the loop computation time • Loop Bound T = t / w • t — loop computation time • w — # of delays in the loop

5. Iteration Bound • Critical Loop — • The loop with the maximum loop bound • Iteration Bound — • Loop bound of the critical loop

6. Iteration Bound • Iteration bound is the lower bound on the sample/clock period of the DSP program regardless of the amount of computing resources available

7. Pipelining & Parallel • Pipelining and parallel are the most important design techniques in VLSI DSP systems • Pipelining — • Different function units working in parallel • Parallel — • Duplicated function units working in parallel

8. Pipelining & Parallel

9. Pipelining • How to do pipelining? • Put pipelining registers across an feed-forward cutset • Drawbacks of Pipelining — • Increasing latency • Increasing the number of registers

10. Parallel

11. Parallel • Drawbacks of Pipelining — • Large hardware cost

12. Retiming • Retiming — • A transformation technique used to change the locations of delay elements in circuit without affecting the input/output characteristics • Applications of retiming — • Reducing the clock period • Reducing the number of registers

13. Retiming • Pipelining is a special case of retiming

14. Retiming • Reducing the clock period —

15. Retiming • Reducing the number of registers —

16. Unfolding • Unfolding is similar to parallel processing

17. Unfolding • Sample/Clock period reduction —

18. Folding