1. ARM architecture Speaker: 陳 育 麟 Advisor: 陳 中 平 教授

2. Outline • Features • Core Interface Signals • 3-stage pipeline organization • Programmer’s Mode • Conditional execution • A basic ARM memory system • ARM instruction set

3. Features • RISC core • Pipelined execution • Load-store architecture • Large uniform register file (R0 ~ R14) • Fixed-length instruction field • Conditional execution of all instructions

4. Core Interface Signals

5. 3-stage pipeline organization

6. 3-stage pipeline organization

7. 3-stage pipeline organization structural hazard!

8. Programmer’s Mode • Visible registers

9. Programmer’s Mode • CPSR I = 1: disable IRQ interruptF = 1: disable FIQ interrupt T = 0: ARM executionT = 1: Thumb execution Negative, Zero, Carry and oVerflow

10. Programmer’s Mode • Exception Vector Address Priorities 1 6 6 5 2 4 3

11. Conditional execution LOOP: … … BNE LOOP;

12. A basic ARM memory system data memory instruction memory

13. A basic ARM memory system • 4-way low order interleaving Size = 1KB

14. ARM instruction set • Branch • Data processing • Status register transferring • Load/Store • Coprocessor • Exception generating (SWI, BKPT)

15. ARM instruction set • B, BL • SyntaxB{L}{<cond>} <target_address>BL: the return address is stored in R14. signed 2-bit interleaving 224 = 16MB ±8MB ±32MB

16. ARM instruction set • BL usage … BL SUB; branch … ; return to here … SUB: … ; subroutine entry … MOV PC, R14; return …CMP R0, #5; if R0 < 5 ; (flag: N,Z,C and V)BLLT SUB1; then call SUB1BLGE SUB2; then call SUB2 …

17. Thank you!