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ARM Introduction & Instruction Set Architecture

ARM Introduction & Instruction Set Architecture

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ARM Introduction & Instruction Set Architecture

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  1. ARMIntroduction &Instruction Set Architecture Aleksandar Milenkovic E-mail: milenka@ece.uah.edu Web: http://www.ece.uah.edu/~milenka

  2. Outline • ARM Architecture • ARM Organization and Implementation • ARM Instruction Set • Thumb Instruction Set • Architectural Support for System Development • ARM Processor Cores • Memory Hierarchy • Architectural Support for Operating Systems • ARM CPU Cores • Embedded ARM Applications

  3. ARM History • ARM – Acorn RISC Machine (1983 – 1985) • Acorn Computers Limited, Cambridge, England • ARM – Advanced RISC Machine 1990 • ARM Limited, 1990 • ARM has been licensed to many semiconductor manufacturers

  4. r0 usable in user mode r1 r2 r3 system modes only r4 r5 r6 r7 r8_fiq r8 r9_fiq r9 r10_fiq r10 r1 1_fiq r1 1 r13_und r12_fiq r13_irq r12 r13_abt r13_svc r14_und r13_fiq r14_irq r13 r14_abt r14_svc r14_fiq r14 r15 (PC) SPSR_und SPSR_irq SPSR_abt CPSR SPSR_svc SPSR_fiq svc abort irq undefi ned fiq user mode mode mode mode mode mode ARM’s visible registers • User level • 15 GPRs, PC, CPSR (current program status register) • Remaining registers are used for system-level programming and for handling exceptions

  5. ARM CPSR format • N (Negative), Z (Zero), C (Carry), V (oVerflow) • mode – control processor mode • T – control instruction set • T = 1 – instruction stream is 16-bit Thumb instructions • T = 0 – instruction stream is 32-bit ARM instructions • I F – interrupt enables

  6. ARM memory organization • Linear array of bytes numbered from 0 to 232 – 1 • Data items • bytes (8 bits) • half-words (16 bits) – always aligned to 2-byte boundaries (start at an even byte address) • words (32 bits) – always aligned to 4-byte boundaries (start at a byte address which is multiple of 4)

  7. ARM instruction set • Load-store architecture • operands are in GPRs • load/store – only instructions that operate with memory • Instructions • Data Processing – use and change only register values • Data Transfer – copy memory values into registers (load) or copy register values into memory (store) • Control Flow • branch • branch-and-link – save return address to resume the original sequence • trapping into system code – supervisor calls

  8. ARM instruction set (cont’d) • Three-address data processing instructions • Conditional execution of every instruction • Powerful load/store multiple register instructions • Ability to perform a general shift operation and a general ALU operation in a single instruction that executes in a single clock cycle • Open instruction set extension through coprocessor instruction set, including adding new registers and data types to the programmer’s model • Very dense 16-bit compressed representation of the instruction set in the Thumb architecture

  9. I/O system • I/O is memory mapped • internal registers of peripherals (disk controllers, network interfaces, etc) are addressable locations within the ARM’s memory map and may be read and written using the load-store instructions • Peripherals may use either the normal interrupt (IRQ) or fast interrupt (FIQ) input • normally most interrupt sources share the IRQ input, while just one or two time-critical sources are connected to the FIQ input • Some systems may include external DMA hardware to handle high-bandwidth I/O traffic

  10. ARM exceptions • ARM supports a range of interrupts, traps, and supervisor calls – all are grouped under the general heading of exceptions • Handling exceptions • current state is saved by copying the PC into r14_exc and CPSR into SPSR_exc (exc stands for exception type) • processor operating mode is changed to the appropriate exception mode • PC is forced to a value between 0016 and 1C16, the particular value depending on the type of exception • instruction at the location PC is forced to (the vector address) usually contains a branch to the exception handler; the exception handler will use r13_exc, which is normally initialized to point to a dedicated stack in memory, to save some user registers • return: restore the user registers and then restore PC and CPSR atomically

  11. C source C libraries asm source C compiler as sembler .aof object libraries linker .axf debug ARMsd system model development ARMulator board ARM cross-development toolkit • Software development • tools developed by ARM Limited • public domain tools (ARM back end for gcc C compiler) • Cross-development • tools run on different architecture from one for which they produce code

  12. Outline • ARM Architecture • ARM Assembly Language Programming • ARM Organization and Implementation • ARM Instruction Set • Architectural Support for High-level Languages • Thumb Instruction Set • Architectural Support for System Development • ARM Processor Cores • Memory Hierarchy • Architectural Support for Operating Systems • ARM CPU Cores • Embedded ARM Applications

  13. ARM Instruction Set • Data Processing Instructions • Data Transfer Instructions • Control flow Instructions

  14. Data Processing Instructions • Classes of data processing instructions • Arithmetic operations • Bit-wise logical operations • Register-movement operations • Comparison operations • Operands: 32-bits wide;there are 3 ways to specify operands • come from registers • the second operand may be a constant (immediate) • shifted register operand • Result: 32-bits wide, placed in a register • long multiply produces a 64-bit result

  15. Data Processing Instructions (cont’d) Arithmetic Operations Bit-wise Logical Operations Register Movement Comparison Operations

  16. Immediate operands:immediate = (0->255) x 22n, 0 <= n <= 12 Shifted register operands the second operand is subject to a shift operation before it is combined with the first operand Data Processing Instructions (cont’d)

  17. ARM shift operations • LSL – Logical Shift Left • LSR – Logical Shift Right • ASR – Arithmetic Shift Right • ROR – Rotate Right • RRX – Rotate Right Extended by 1 place

  18. Setting the condition codes • Any DPI can set the condition codes (N, Z, V, and C) • for all DPIs except the comparison operations a specific request must be made • at the assembly language level this request is indicated by adding an `S` to the opcode • Example (r3-r2 := r1-r0 + r3-r2) • Arithmetic operations set all the flags (N, Z, C, and V) • Logical and move operations set N and Z • preserve V and either preserve C when there is no shift operation, or set C according to shift operation (fall off bit)

  19. Multiplies • Example (Multiply, Multiply-Accumulate) • Note • least significant 32-bits are placed in the result register, the rest are ignored • immediate second operand is not supported • result register must not be the same as the first source register • if `S` bit is set the V is preserved and the C is rendered meaningless • Example (r0 = r0 x 35) • ADD r0, r0, r0, LSL #2 ; r0’ = r0 x 5RSB r3, r3, r1 ; r0’’ = 7 x r0’

  20. Data transfer instructions • Single register load and store instructions • transfer of a data item (byte, half-word, word) between ARM registers and memory • Multiple register load and store instructions • enable transfer of large quantities of data • used for procedure entry and exit, to save/restore workspace registers, to copy blocks of data around memory • Single register swap instructions • allow exchange between a register and memory in one instruction • used to implement semaphores to ensure mutual exclusion on accesses to shared data in multis

  21. Data Transfer Instructions (cont’d) Register-indirect addressing Single register load and store Note: r1 keeps a word address (2 LSBs are 0) Base+offset addressing (offset of up to 4Kbytes) Note: no restrictions for r1 Auto-indexing addressing Post-indexed addressing

  22. Data Transfer Instructions (cont’d)

  23. Block copy view data is to be stored above or below the the address held in the base register address incrementing or decrementing begins before or after storing the first value Data Transfer Instructions Multiple register data transfers Note: any subset (or all) of the registers may be transferred with a single instruction Note: the order of registers within the list is insignificant Note: including r15 in the list will cause a change in the control flow • Stack organizations • FA – full ascending • EA – empty ascending • FD – full descending • ED – empty descending

  24. Multiple register transfer addressing modes 1018 1018 r9’ r9’ r5 16 16 r5 r1 r1 r0 r9 r0 100c r9 100c 16 16 1000 1000 16 16 STMIA r9!, {r0,r1,r5} STMIB r9!, {r0,r1,r5} 1018 1018 16 16 r9 r5 100c r9 100c 16 16 r1 r5 r0 r1 1000 1000 r9’ r9’ r0 16 16 STMDA r9!, {r0,r1,r5} STMDB r9!, {r0,r1,r5}

  25. The mapping between the stack and block copy views

  26. Control flow instructions

  27. Conditional execution • Conditional execution to avoid branch instructions used to skip a small number of non-branch instructions • Example With conditional execution Note: add 2 –letter condition after the 3-letter opcode

  28. Branch and link instructions • Branch to subroutine (r14 serves as a link register) • Nested subroutines

  29. Supervisor calls • Supervisor is a program which operates at a privileged level – it can do things that a user-level program cannot do directly • Example: send text to the display • ARM ISA includes SWI (SoftWare Interrupt)

  30. Jump tables • Call one of a set of subroutines depending on a value computed by the program Note: slow when the list is long, and all subroutines are equally frequent

  31. Hello ARM World!

  32. ARMOrganization and Implementation Aleksandar Milenkovic E-mail: milenka@ece.uah.edu Web: http://www.ece.uah.edu/~milenka

  33. Outline • ARM Architecture • ARM Organization and Implementation • ARM Instruction Set • Architectural Support for High-level Languages • Thumb Instruction Set • Architectural Support for System Development • ARM Processor Cores • Memory Hierarchy • Architectural Support for Operating Systems • ARM CPU Cores • Embedded ARM Applications

  34. ARM organization A[31:0] control address register • Register file – • 2 read ports, 1 write port + 1 read, 1 write port reserved for r15 (pc) • Barrel shifter – shift or rotate one operand for any number of bits • ALU – performs the arithmetic and logic functions required • Memory address register + incrementer • Memory data registers • Instruction decoder and associated control logic P incrementer C PC register bank instruction decode A multiply & L register U control A B b u b b s u u barrel s s shifter ALU data out register data in register D[31:0]

  35. Three-stage pipeline • Fetch • the instruction is fetched from memory and placed in the instruction pipeline • Decode • the instruction is decoded and the datapath control signals prepared for the next cycle; in this stage the instruction owns the decode logic but not the datapath • Execute • the instruction owns the datapath; the register bank is read, an operand shifted, the ALU register generated and written back into a destination register

  36. ARM single-cycle instruction pipeline

  37. decode execute add fetch decode execute sub fetch decode ARM single-cycle instruction pipeline fetch add r0,r1,#5 sub r2,r3,r6 execute cmp cmp r2,#3 time 1 2 3

  38. ARM multi-cycle instruction pipeline Decode logic is always generating the control signals for the datapath to use in the next cycle

  39. ARM multi-cycle LDMIA (load multiple) instruction Decode stage occupied since ldmia must continue to remember decoded instruction fetch decode ex ld r2 ex ld r3 ldmia r0,{r2,r3} sub r2,r3,r6 fetch decode ex sub fetch decode ex cmp cmp r2,#3 time Instruction delayed sub fetched at normal time but not decoded until LDMIA is finishing

  40. Control stalls: due to branches • Branches often introduce stalls (branch penalty) • Stall time may depend on whether branch is taken • May have to squash instructions that already started executing • Don’t know what to fetch until condition is evaluated

  41. fetch decode ex bne ex bne ex bne bne foo sub r2,r3,r6 fetch decode fetch decode ex add foo add r0,r1,r2 ARM pipelined branch Decision not made until the third clock cycle Two cycles of work thrown away if bne takes place time

  42. Pipeline: how it works • All instructions occupy the datapath for one or more adjacent cycles • For each cycle that an instruction occupies the datapath, it occupies the decode logic in the immediately preceding cycle • During the fist datapath cycle each instruction issues a fetch for the next instruction but one • Branch instruction flush and refill the instruction pipeline

  43. next pc + 4 I-cache fetch pc + 4 pc + 8 I decode instruction r15 decode register read immediate fields mul LDM/ STM post- index +4 reg shift shift execute pre-index ALU forwarding paths mux B, BL MOV pc SUBS pc byte repl. buffer/ D-cache load/store data address rot/sgn ex LDR pc write-back register write ARM9TDMI 5-stage pipeline • Fetch • Decode • instruction is decoded • register operands read (3 read ports) • Execute • an operand is shifted and the ALU result generated, or • address is computed • Buffer/data • data memory is accessed (load, store) • Write-back • write to register file

  44. next pc + 4 I-cache fetch pc + 4 pc + 8 I decode instruction r15 decode register read immediate fields mul LDM/ STM post- index +4 reg shift shift execute pre-index ALU forwarding paths mux B, BL MOV pc SUBS pc byte repl. buffer/ D-cache load/store data address rot/sgn ex LDR pc write-back register write ARM9TDMI Data Forwarding Data Forwarding Stall?

  45. next pc + 4 I-cache fetch pc + 4 pc + 8 I decode instruction r15 decode register read immediate fields mul LDM/ STM post- index +4 reg shift shift execute pre-index ALU forwarding paths mux B, BL MOV pc SUBS pc byte repl. buffer/ D-cache load/store data address rot/sgn ex LDR pc write-back register write ARM9TDMI PC generation • 3-stage pipeline • PC behavior: operands are read in execution stage r15 = PC + 8 • 5-stage pipeline • operands are read in decode stage and r15 = PC + 4? • incompatibilities between 3-stage and 5-stage implementations => unacceptable • to avoid this 5-stage pipeline ARMs emulate the behavior of the older 3-stage designs

  46. address register address register increment increment Rd PC Rd PC registers registers Rn Rm Rn mult mult as ins. as ins. as instruction as instruction [7:0] data out data in i. pipe data out data in i. pipe Data processing instruction datapath activity (Ex) • Reg-Reg • Rd = Rn op Rm • r15 = AR + 4AR = AR + 4 • Reg-Imm • Rd = Rn op Imm • r15 = AR + 4AR = AR + 4 (a) register – register operations (b) register – immediate operations

  47. address register increment Rn PC registers Rd mult shifter = A + B / A - B byte? data in i. pipe STR (store register) datapath activity(Ex1, Ex2) • Compute address (Ex1) • AR = Rn op Disp • r15 = AR + 4 • Store data (Ex2) • AR = PC • mem[AR] = Rd<x:y> • If autoindexing=>Rn = Rn +/- 4 address register increment PC registers Rn mult lsl #0 = A / A + B / A - B [11:0] data out data in i. pipe (b) 2nd cycle – store data & auto-index (a) 1st cycle – compute address

  48. address register address register increment increment R14 registers registers PC PC mult mult shifter lsl #2 = A = A + B [23:0] data out data in i. pipe data out data in i. pipe The first two (of three) cycles of a branch instruction • Compute target address • AR = PC + Disp,lsl #2 • Save return address (if required) • r14 = PC • AR = AR + 4 Third cycle: do a small correction to the value stored in the link register in order that it points to directly at the instruction which follows the branch? (b) 2nd cycle – save return address (a) 1st cycle – compute branch target

  49. ARM Implementation • Datapath • RTL (Register Transfer Level) • Control unit • FSM (Finite State Machine)

  50. 2-phase non-overlapping clock scheme • Most ARMs do not operate on edge-sensitive registers • Instead the design is based around 2-phase non-overlapping clocks which are generated internally from a single clock signal • Data movement is controlled by passing the data alternatively through latches which are open during phase 1 or latches during phase 2