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DSP Builder v5.1.0

DSP Builder v5.1.0. October 2005. Prerequisites. Understanding of DSP Builder Understanding of Simulink Understanding of SOPC Builder and Avalon Interface Specification Understanding of IP MegaCore Design Flow Understanding of Quartus II. Agenda . DSP Builder Overview

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DSP Builder v5.1.0

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  1. DSP Builder v5.1.0 October 2005

  2. Prerequisites • Understanding of DSP Builder • Understanding of Simulink • Understanding of SOPC Builder and Avalon Interface Specification • Understanding of IP MegaCore Design Flow • Understanding of Quartus II

  3. Agenda • DSP Builder Overview • New Features in DSP Builder v5.1.0 • Enhancements • Known Issues • Conclusion

  4. Overview

  5. System Level Design Tool Verification Development Implementation System Level Simulation of Algorithm Model MATLAB/Simulink RTL Implementation RTL Simulation Leonardo Spectrum Precision, Synplify Quartus II, ModelSim System Level Verification of Hardware Implementation Hardware Single Simulink Representation Algorithm Modeling System-level Verification Synthesis, Place ‘n Route, RTL Simulation System Algorithm Design and FPGA Design Integrated

  6. Place and Route Creates HDL Code Creates Simulation Testbench Download Design to DSP Development Kits Verify in Hardware DSP Builder Overview HDL Synthesis Creates SOPC Builder Ready Component

  7. Version Compatibility Note (*) MATLAB/Simulink R13: Matlab v6.5, Simulink v5.0 MATLAB/Simulink R14: Matlab v7.0, Simulink v6.0 MATLAB/Simulink R14SP1: Matlab v7.0.1, Simulink v6.1 MATLAB/Simulink R14SP2: Matlab v7.0.4, Simulink v6.2 MATLAB/Simulink R14SP3: Matlab v7.1, Simulink v6.3

  8. New Features

  9. DSP Builder v5.1 New Features • HDL Import • Enhanced SOPC Builder Integration • Support Multiple Versions of IP MegaCores • Bit Width Parameterization • Name Propagation

  10. HDL Import

  11. Import VHDL, Verilog or Quartus II Project Simulink Simulation Model is Automatically Generated Allows Co-Simulation Does Not Require 3rd Party Simulator Allow Multiple Instantiations HDL Import

  12. HDL Import Interface • Supports Hierarchical Designs with Multiple Entities • Add Verilog/VHDL Files or Select Quartus II Project • Set Top-Level Entity (Verilog or VHDL only) • Compile • Generate Simulink Model

  13. HDL Import Requirements • Single Clock Domain • Synchronous Design • Supports Generic Memory and Logic Functions • Logic Elements • Memory • DSP Blocks • Does Not Support Device Specific Functions • Examples - PLL, LVDS, WYSIWYG • Refer to DSP Builder Reference Manual for Complete List of Supported MegaFunctions

  14. Design Flow using HDL Import

  15. What About SubSystemBuilder? • Import HDL File • User Creates Own Simulation Model • Speed Up Simulation Using Own Simulink Model • Can Use SubSystemBuilder If Design Contains Unsupported LPMs/MegaFunctions

  16. Comparison of HDL Co-Design Features Note: (1) User creates their own Simulink simulation model. Simulation speed depends on the type of simulation model.

  17. Enhanced SOPC Builder Integration

  18. SOPC Builder Integration • User Can Build Any Avalon SOPC Component • Dragging and Dropping Avalon Interfaces into DSP Builder Design • Validate by Simulating in Simulink • Export to SOPC Builder by Generating HDL and PTF from Signal Compiler

  19. Enhanced SOPC Builder Integration • Interface Blocks • Avalon Slave • Avalon Master • Wrapped Blocks • Avalon Read FIFO • Avalon Write FIFO • Multiple Slaves and Masters • Advanced Avalon Bus Support

  20. Interface Blocks • Low-level Access to Avalon Signals • All Ports have “Pass-Through” Behaviour • Allows Multiple Slaves/Masters • Mechanism for setting PTF variables • Dialog to Configure Mode of Operation Avalon Slave Avalon Master

  21. Avalon Master • User Configurable to Allow Subset of Signals • Modes of Operation • Flow Control • Pipeline Transfers • Burst Transfers

  22. Avalon Master Signals

  23. Input Avalon Master Example Output

  24. Avalon Slave • User Configurable to Allow Subset of Signals • Modes of Operation • Flow Control • Pipeline Transfers • Burst Transfers

  25. Avalon Slave Signals

  26. Input Avalon Slave Example Output

  27. Wrapped Blocks • Higher Level of Abstraction • Map Avalon Signals to a “Standard” Subset • Both Read/Write FIFOs Handle Streaming Data • Test Avalon Interface in Simulink Environment Avalon Write FIFO Avalon Read FIFO

  28. Avalon Write FIFO • Hierarchical Component • Configuration Dialog • Data Type • Data Width • FIFO Depth

  29. Avalon Write FIFO Internals • Look Under Mask • User Can Customize Functionality using Mask Editor

  30. Avalon Write FIFO Signals

  31. Avalon Read FIFO • Hierarchical Component • Configuration Dialog • Data Type • Data Width • FIFO Depth

  32. Avalon Read FIFO Internals • Look Under Mask • User Can Customize Functionality using Mask Editor

  33. Avalon Read FIFO Signals

  34. Testing Blocks • Streaming Avalon Converter • Provides Data to Avalon Write FIFO • Collects Data from Avalon Read FIFO • Not Synthesizable

  35. Avalon Write/Read FIFO Example

  36. Simulink Simulation • Avalon Blocks Accept Simulink Data • Use Standard Simulink Source/Sink Blocks

  37. HDL and PTF Generation • Set Option to Generate PTF in Signal Compiler • VHDL Entity/Port Names Derived From Block • PTF File Automatically Generated • Needed for Import in SOPC Builder • Component Appears in SOPC Suite

  38. SOPC Builder System Editor Nios II H/W Core + DMAs

  39. What About Avalon Ports? • Only For Legacy Design • Allow One Slave Per Design • Avalon Slave Block Has Same Functionality • Except for Chip Select

  40. Other New Features

  41. IP MegaCore Support • Access to Multiple Versions of IP • Versioned MegaCore • Blue Color • Recommended for New Designs • Legacy MegaCore • Gray Color • For Backwards Compatibility • Warnings Will Be Generated Example: Warning: The block ‘test/csc' is linked to 'MegaCoreAltr/csc', which is a legacy block in the library and should not be used in new designs.

  42. Update IP MegaCore • Automatic Update • Global Update • Create Two Variables in MATLAB • dspbuilder_reinstall_megacores = ‘on’ • dspbuilder_auto_update_megacore=‘on’ • Rerun setup_dspbuilder • Update MDL (Edit Menu) or Ctrl-D • Manual Update • Design Specific Update • update_megacores [design_name]

  43. Design Parameterization Support 5.1 5.0 • User can explore design optimization possibilities

  44. Propagation of Signal Names

  45. Enhancements

  46. DSP Builder v5.1 Enhancements • Error Message Improvements • Simulation Performance Enhancements • Documentation Improvements

  47. Improved Error Messaging Hyperlinks in MATLAB command window Blocks causing error are highlighted

  48. IP Simulation • Simulation Time Speed Up • Typically ~20% Faster • Improved Memory Usage • Previously Memory Grew Linearly During Simulation, Limiting Simulation Time • Less Variation in Simulation Time • Previously > 2x Difference in Run-Time Possible for Identical Simulations • Now Always Minimum

  49. Documentation Improvements • Integrated with Matlab help

  50. Known Issues

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