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SVT detector Electronics Status

SVT detector Electronics Status. Mauro Villa INFN & Università di Bologna. Overview: - SVT design status - F.E. chips - Electronic design - Hit rates and data volumes - TDR. 1. SVT Design. Detectors : 5 Layers with Si Strips (z, phi, L1-L5); one high precision inner layer (L0)

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SVT detector Electronics Status

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  1. SVT detector Electronics Status Mauro Villa INFN & Università di Bologna Overview: - SVT design status - F.E. chips - Electronic design - Hit rates and data volumes - TDR 1

  2. SVT Design Detectors: 5 Layers with Si Strips (z, phi, L1-L5); one high precision inner layer (L0) Open options for L0: striplets (45° strips), Hybrid pixels, MAPS Front-End Chips: 128 channels ASIC for strips, large (>10k) pixel area chip ROS: Layers are segmentend in phi (8-18) and z (2): 240 Read-Out Sections (ROS) 2

  3. Strip/Striplet front-end chips • ASIC to be build based on previous experiences in several fields: • FSSR2 chip (analog part), SuperPix0, ApselXD (readout architecture) • CERN experience on specific blocks: Voltage regulators, serializers. • Develop fast (L0-L3) and slow (L4-5) channels (analog part tuning). • Triggered only chip with tunable time stamp characteristics. • Serialized output to reduce the I/O line count • Full VHDL simulation for TDR • prototype chips in 2012 & 2013; • production in 2014 POF: the first derandomizer is in FE chips 3

  4. Pixel chips for L0 Apsel-VI (MAPS) MATRIX 96x128(2 sub-m. 48 x128) Rows divided in: 4 sparsifiers 32 rows for each sparsifier SuperPix1 (hybrid pixels) MATRIX 32x128 (2 sub-m. 16x128) Rows divided in: 4 sparsifiers 32 rows for each sparsifier • Triggered chips; L1 latency on pixels; efficiencies >98%; • Output rate max: 200 MHit/s; • To be submitted on 26th march 2012 4

  5. DAQ reading chain for L0-L5 DAQ chain independent on the chosen FE options Optical 1 Gbit/s Example of a read-out section Front-end chips Optical Link 2.5 Gbit/s to ROM UPILEX+Cu (?) FEB C Copper bus Serdes or FPGA Detector fibers HDIs ~1-2 m LV1 Transition card High rad area 15Mrad/year Off detector low rad area Counting room Std electronics HDI card design is ongoing Data Encoder IC .... Specs are under discussion Rad-hard serializer to be finalized  looking into a low power/low speed version Copper tail: lenght vs data transfer are under study FEB + ROM as before 5

  6. L0 Pixel option - Bus status Data lines • Production of BUS is finally starting • The layout is final and «single» layers are at the beginning of the production • Production will take approximately 5 weeks M. Citterio Frascati, Dec 2011

  7. L0 striplet option - Fan-out • First exercise made using CERN information • Two layer of Kapton (20 um) + Aluminum (10um) +Glue(10 um) … … … … W=12.9 mm Staggering to compensate pitch towards ICs … … … … L=97.0 mm 50 um pitch Drawing not to scale !!!! 173 shorter strips Module thickness: ≈0.05% Xo Frascati, Dec 2011

  8. L1-L5 Detector – Connection HDI Low rate – 1 ouput line/FE chip Z Z φ High rate N lines/FEC 9

  9. HDI and output bus Rad-hard characteristics dependent on chips Requirement: > 5 Mrad/year Power dissipation: < 1 W/chip (guess-estimate, past values) Option for a serializer on HDI Minimal number of elements on HDI (ideally only FE chips and possibly a serializer) 6 shared input lines: Reset, Clock, FastClock, Timestamp, Trigger, RegIn 1 shared output line: RegOut N lines x M chips in output (N:1-6, M: 4-10) Ground and powering on the bus Signal lines in standard LVDS (CMOS to/from LVDS required on HDI if not provided on FE) φ High rate N lines/FEC 10

  10. Transition card Role of the Transition card: Provide an interface between FE and DAQ system Switch between copper and optical link data transmission Forward power to FE chips Serdes or FPGA Off detector low rad area • Several open options: • Optical link • Intrinsic dual link preferred: GBT (?), GOLx2 (?) • Single link option possibile (data output link) together with a chip input data system (FCTS?) • Fast Des/Serdes • SMU (Dallas), 5 Gbps, 500 mW (rad-hard) • Other Des/Serdes ? • FPGA (very interesting in principle, but not rad-hard [for the moment?]) • Studies on ATMEL IC qualified for space (rad-hard) 11

  11. Data/Clock and Control Cables Signal: 39 AWG, Bifilar magnet wires (Cu) Differential Impedance: to be measured Capacitance: 75 pF/m Propagation Delay: to be measured Dielectric costant: 2.1 Twisting is not needed for such a small wire It can not be purchased in tape - grouping of individual wires could introduces signal degradation  NSQP project at CERN Electrical test on individual pair is starting - on individual wires - on few (up to 10 couples) wires with or without a braid Option for one line/ROS, Serdes on hybrid M. Citterio Frascati, Dec 2011

  12. SuperB-FEB Board schematics Request: 2 9U-VME crates Behind Rad-wall Gb ethernet Large FPGA VME! DAQ link 2.5 Gbit/s VME FPGA Or uCPU L1/Spare DAQ link 4x1 Gbit/s FE links FCTS interface Small FPGA 4x1 Gbit/s FE links ECS interface Memory Small FPGA 4x1 Gbit/s FE links Small FPGA FCTS, ECS protocols to be decided experiment-wide Large FPGA for data shipping and monitoring VME FPGA or uCPU might be included in the large FPGA. POF: the second Derandomizer is in FEB 13

  13. Hit and Trigger generation and read out Bare Assumptions: Readout clock: 60 MHz Time stamp clock: 30 MHz Trigger rate: 150 kHz Fully triggered SVT DAQ Acquisition window: 300 ns (L0-L3), 1 us (L4-L5) Latency <10 us Buffers in chip and in reading chain wide enough for eff>99.8% Optical link 1 Gbit/s ; 2.5 Gbit/s to ROM Background rates from latest BRUNO simulations with safety factors 5 14

  14. SVT Background rates R. Cenci, dec 2011 Background simulation: • Strip detail implemented in Bruno for a more accurate rate calculation Data volumes and bandwidths SVT data volumes and bandwidths are mostly independent on the details of the design, but are defined mainly by background, trigger rates and DAQ time windows. 15

  15. SVT Data rates, links and boards R. Cenci, sep 2011 MC Needs: 172 1-Gbps links, 18 Front-End Boards 2.5 Gbps links usable with load balancing connections (or data compression). Average event size: 24 kB. 16

  16. TDR – SVT readout electronics Readout chain schema and reference to the relevant SVT parts (FE and hybrids) (Transition card) Serializers / Links / Trigger ) Design of the Readout Card Input data links/Data compression/Output links Fast (Trigger) and slow (configuration) signals handling Data rates and data volumes

  17. Summary SVT electronic has several open options at the moment - L0 type: striplet/hybrid pixels/MAPS - Strip FE chips have to be designed (architectures ready, simulations ongoing) - Reduced size pixel FE chips to be submitted in march 2012 One fix: triggered only chips everywhere. Major (ETD common) unknowns: 1 Gbps optical link types (bidirectional? To be defined by ETD ) Serdes/FPGA (To be defined by ETD ) Additional active elements in the HDI (Rad-hardness tests to be made) DAQ chain is progressing by defining all the elements of the chain No showstopper seen in the “upper” part: FEB & ROMs. 18 17

  18. Questionarie SuperB integration question naire Data: 5/11/2011 Sub detector name: SVT Author: Electronics: input from Villa Citterio Re Bettarini Number of electronic channel: 1) Internal chips: ≈2200 FE chip, 172x2 ser/des encoding, 172x2 optical link 2) 172 Transition boards at 1 m from SVT (just outside the detector?) 3) 18 FEB boards behind the radiation walls 4) Power supply boards outside (?) Power dissipated per channels: 1) 0.1 mW/chip, serdes and links to be decided 2) unknown 3) unknown 4) unknown Volume occupied by the electronics (drawings of electronic modules): 2) Design and exact place to be defined; 3) 2 9-U VME crates 16 12/21/2019

  19. Questionarie Max tolerable distances between the detectors to the electronic modules: 1 meter between FE chips and Transition card 50 meters between Transition card and FEBs (in a VME crate) 10 meters between Power supply and Transition cards Access frequency on the external electronic per year: What are the needs? 2 times/year to measure I-V bypassing PS? ?? Frequency access on the detector per year: Only in case of accident 17 12/21/2019

  20. Questionarie Cables: input from Citterio, Villa Number and size of power cable: input from babar are reasonable ? From inside to FEB and from FEB to PS Number and size of Read-out cables or fibers: Fibers: 172 bidirectional, 1 Gbps fibers, length 50 m (?) Fibers: 18 bidirectional, 2.5 Gbps fibers, length 3-5 m (?) Number and size of slow control cables: If bidirectional links, just clock distribution is needed. 172 special buses to go from transition card to FE chips. (1-2m with 1-2 cm width, <1mm thickness) Minimum bending radius. Shielding requirements (thermal and electrical) Citterio Information drawings on the cable distribution on the detector geometry: Can use babar schema as starting point 18 12/21/2019

  21. Backups 19

  22. Data/Clock and Control Cables Signal: 30 AWG, Solid Copper Clad Aluminum Differential Impedance ~ 100 Ohms +/- 5% Capacitance: 16 pF / ft Propagation Delay: < 2 ns/ft The preliminary measurements show that LOC1 can drive such a cable without substantial degradation even without pre/post emphasis Eye diagram BER probability density function 10 23 La Biodola 2011 Mauro Citterio

  23. Data/Clock and Control Cables (1 of 2) Kapton tail is probably not a solution for SuperB - data speed is much higher than before - differential/coaxial lines are not usually designed in flat circuits Some small and flexible cables have been selected and tests are on-going Some preliminary studies are ongoing (see M. Citterio talk in LONDON) - the reference lenght has been chosen ~ 1m (not to push on driving capability of devices) - the test has been performed using - Xilinx FPGA + Rocket IO as a reference - Xilinx FPGA + LOC1 serializer as a comparison 9 24 La Biodola 2011 Mauro Citterio

  24. Readout architectures Few revisions w.r.t. INMAPS architecture. In-pixel threshold adjust DAC serial vs I2C loading? I2C very time-expensive for protocol overhead, till now used to program the peripheral registers and to mask the few defective pixels here and there. Meant for the slow control of several chip with 2 shared serial lines, not to transfer large amount of data (~ 250k bit for the big chip). New component proposed by PV/BG: Internal pulser for Gain scans No external pulser needed, digitally controlled. Peripheral DAC to trimmer the pulses An additional mixed signal component in the floorplan  needs Physical synthesis of std. cells and interconnection to peripheral RO. Injection mask loading? (see above) Possible in principle. I need to investigate HOW. 25

  25. Strip FE chip output stage Assumption: 16 bits data words 7 strip id; 4 tot; 1 hit/TS; 4 redundancy 10 Time stamp; 1 hit/TS; 5 redundancy Trigger rate: 150 kHz, BCO 30 MHz, DAQ win:300 ns

  26. Configuration and open options Layer0 20 cm 30 cm 40 cm LayerRadius 0 ~1.5 cm 1 3.3 cm 2 4.0 cm 3 5.9 cm 4 9.1 to 12.7 cm 5 11.4 to 14.6 cm Layer 0 • Striplets baseline option : • Better physics performance (lower material ~0.5% vs 1% hybrid pixel, MAPS or thin hybrid pixel in between but not yet mature!) • Upgrade to pixel (Hybrid or CMOS MAPS), more robust against background, foreseen for a second generation of Layer0 Triggered FE chips Layer 1-5 • Strip detectors (up to 37 cm long) Triggered FE chip in the design phase 20

  27. SVT- Electronic status ~hit_rate * trig_latency Sparsifier strip #127 FE ADC Or ToT Ctrl logic Buf #k ... Buf #1 strip #0 FE ADC Or ToT Ctrl logic Buf #k ... Buf #1 BUF #1 Triggered hits only readout/slow control Layer 0 Triggered FE chips • Striplets baseline option : • Better physics performance  Readout chip in the planning phase • Upgrade to pixel, more robust against background, foreseen for a second generation of Layer0  Readout chip designed Triggered FE chips Layer 1-5 • Strip detectors  Readout chip in the planning phase DAQ Chain main activities Strip RO chip RadHard SerDes needed 21

  28. Pixel front-end chips (L0) Full design of a 256x192 pixel matrix (50 um pixel width) running at 70 MHz; Timestamping at 100 ns; output clock at 200 MHz Data push or data pull selectable working mode 2 1 22 X4

  29. 1-st prototypes results Bus for pixel chips Aliminum on kapton 165 um • Pixel Bus Prototype measurements: • Thermal test on the BUS did not show problems up to 85-90 Centigrade • A typical impedance of ~ 60 Ohm confirmed • Crosstalk higher than simulated ~ 5 %  Measurements performed on various samples with same results • frequency response: • signal transferrred with no “digital errors” up to 200 MHz, on individual lines (pattern ex. 0000100) • if a random digital pattern is sent through 8 adjacent lines, than max frequency decreases at ~ 160 MHz (line lenght ~ 10 cm) 24 M. Citterio 30 Apr. 2011 Mauro Citterio

  30. Bus for pixel chip - II • Pixel Bus second generation: • Layout details agreed • Production: it could have started week 7 •  Production conclusion estimate  8-10 week later • Cern suggestions: Review the signal layers: concern about 15 um Al layer and 75 um lines prefer a BUS with decreased thickness Adoption of Cu (3 um thick, 50 um wide) • Simulation performed • on a 1101 pattern (three aggressors and one victim, the “0” line) • The results refer to the longest stripline. Goal was to keep the crosstalk signal below +/- 200 mV • The maximum frequency is ~ 130 MHz • There is no optimal termination at the receiving end. • Driver and receiver are implemented using the IBIS models provided by Xilinx • BUS bandwidth is decreased by ~ 15 % • It is the worst case ? Two IC signals will share the same plane 25 M. Citterio

  31. Readout chip for strips ~hit_rate * trig_latency Sparsifier strip #127 FE ADC Or ToT Ctrl logic Buf #k ... Buf #1 strip #0 FE ADC Or ToT Ctrl logic Buf #k ... Buf #1 BUF #1 Triggered hits only readout/slow control First buffering per strip then transfer triggered time stamps Re-use of digital readout logic developed for pixels 26

  32. Analog part: ENC, shaping time and efficiency estimates RC2CR shaping, ID=500 mA (current in the PA input device), L=200 nm, N-channel input device, analog dead time=2.4 tp 27 V. Re SuperB Workshop, Frascati, April 4, 2011 33

  33. First guess on number of buffers required for L0 striplets/L1 strip Assume L0 @ 225 MHz/cm2, L1@5 MHz/cm2 L0 = 2 MHz/strip, L1=270 KHz/strip 28 F. Morsani

  34. DAQ reading chain for L0-L5 HDI +Transition card+FEB+ROM DAQ chain independent on the chosen FE options Optical 1 Gbit/s Optical Link 2.5 Gbit/s ~50 cm FEB ROM LV1 High rad area 10Mrad/year Off detector low rad area Counting room Std electronics HDI and transition card to be designed. Which SerDes? 29 35

  35. Optical link mezzanine card for EDRO Developed as a part of ATLAS/FTK project 4 optical links at 1 Gbit/s; FPGA Xilinx, 40/100 MHz clk (programmable) PCB realized; now mounting components on first prototype Usable as link test mezzanine in SuperB (from autumn) 30

  36. Summary Slide next!

  37. SVT summary

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