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NASA EEPROM Workshop October 12, 2005

NASA EEPROM Workshop October 12, 2005. Presentation by Austin Semiconductor Inc Jeff Kendziorski. Table of Contents. “I want to thank-you for making this day necessary” -Yogi. Introduction Austin Semiconductor in 2-minutes What is being presented: Thermal Conditioning during I/C Test

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NASA EEPROM Workshop October 12, 2005

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  1. NASA EEPROM WorkshopOctober 12, 2005 Presentation by Austin Semiconductor Inc Jeff Kendziorski

  2. Table of Contents “I want to thank-you for making this day necessary” -Yogi • Introduction • Austin Semiconductor in 2-minutes • What is being presented: • Thermal Conditioning during I/C Test • Read Cycle Endurance Exercise • F/A single bit cold fail • Life Test Summary • Hitachi Reliability Data’s & Current Density • 58C1001 Architecture & Topology • Basic Layout • Byte vs Page Write • TOPO Scramble / Bit-Mapping • Laser Repair & Redundancy • Reset pin operation & tester experiment • Data Retention/Endurance • Weak Bit / Margin Screening • Steps to consider for achieving highest reliability for 58C1001 Space use • GIDEP Advisory comments • Conclusion/Summary 10/12/05 /jk

  3. Factory Contacts • President: Neil Duarte • office ph# (512) 719-7252 • email addr: nduarte@austinsemiconductor.com • VP of Quality: Glenn Frashure • office ph# (512) 719-7276 • email addr: gfrashure@austinsemiconductor.com • Director of Engineering: Jeff Kendziorski • office ph# (512) 719-7254 • email addr: jkendziorski@austinsemiconductor.com 10/12/05 /jk

  4. Austin Semiconductor Company Snapshot • Company Started in 1988 Focused on SPACE Custom packaging, assembly & test • still a mainstay of our business , over 1500+ unique parts • Became Standard Military Memory supplier w/ Micron(94) & TI(99) Military Memory Line Purchases. ‘Kit & Kaboodle’ • First Aftermarket Supplier QML certification for Mil-Prf-38535 (Class Q & V level) • since added Modules cert Mil-Prf-38534(1999), ISO 9001/9002, DSCC Lab suit • Privately help company, owed by PMC (http://www.pmcglobalinc.com) • 40+ companies, >$800M revenue ASI part of ASC electronics group of 5 companies • ASI became part of PMC in 1994 • In-house full flow 1-stop shop for Mil/Space Flows & Quals(Mil-Std-883) • Recent additions of HAST & Autoclave Chamber, ESD tester boot-straps COTs plastic support • Increasing COTs plastic focus along with Service Support & Characterization 10/12/05 /jk

  5. Contracted by customer Determine if EEPROM Read Cycle limited Customer Board designed on board logic to drive addr sequence RES/ low for both PU & PD CE/, OE/, WE/ Tied to VCC Total Dummy Reads to entire Array: 348x106 147 days, Verify Array every 7th day March Addr Sequence VCC=5V, Temp = 50C Read cycles = ~3.6Mhz Random Array pattern Total of 22 device RESULTS: 22/0 (used/fail) 21 read points, NO fails at any. Read Cycle Endurance Exercise 10/12/05 /jk

  6. Customer Return for -30C S/B Fail 1 die on 128Kx32 MCM w/ 4 die total Mapped out single bit Address & DQ Determine Symptoms of fail failed to hold ‘0’ programmed state Pass at -20C, Fail at -30C Process De-layering to ID defect Physical location isolated * NOT a Simple Matter * Address scrambled Logical to Physical translation Package routing Redundancy Caution ! Micro-probing with EBIC insitu in SEM provides added confidence in location Great tool for this die because of near-Zero ICCq Deprocessing by Analytical Solutions Inc Defect identified in the Tunnel OX Wafer Fab process defect resulted in weak cell for tunneling electrons reduced charge with temperature threshold Most Probable Cause test escape, operator mishandling or thermal op. F/A of Single Bit RMA failure (I of II) 10/12/05 /jk

  7. F/A of Single Bit RMA failure (I of II) 10/12/05 /jk

  8. Summary of AS58C1001 Life Tests * Space level Flows * Read& Read & Delta measurements included * sample of data available 10/12/05 /jk

  9. Hitachi 58C1001 Reliability Data’s 49FITS Calc in Hitachi lit Est of Hard Fail, w/ .4eV Ea 10/12/05 /jk

  10. Mil Spec 2x105 A/cm2 Hitachi Design est 6.25x104 A/cm2 Hitachi EEPROM Process Rule 1x105 stated in email response typ contact size 3um typ Bit Lines 0.90um Multiple contacts employed Metal Thickness MoSi(Cap) 60nm AlCuSi 800nm MoSi(barrier) 30nm 58C1001 Current Density 10/12/05 /jk

  11. 58C1001 Design Architecture

  12. 58C1001 Topology ‘Scramble’ * Octal A/A* sequence * Consecutive I/O’s in same address * Note Redundancy -both row & column * What is a Dummy Word? * Bit-Mapping 10/12/05 /jk

  13. Byte vs Page Mode 10/12/05 /jk

  14. 58C1001 Laser Repair & Redundancy • Early 90’s .8um minimum feature CMOS design • Employ’s Laser Repair & Redundancy to improve probe yield • Repair S/B, Multi S/B if close proximity, sm cluster, full row & full column • Typical Percentage Die with repair is 20%(+/-10) of the “natural” GED’s • Varies depending on lot dependance & defects for given lot AND PROCESS MATURITY or lackof. • Both Row & Column redundancy options implied in floor plan(no design info rec’vd) • Bad Row or Bad Column NOT physically removed • still has power, just disabled • Only Logical replacement of bad rows/columns only • Typically a block will be logically replaced (8, 16 or 32 addressable cells) • Need about 500X+ to visually inspect blown fuse(typically a poly material) 10/12/05 /jk

  15. RES/ & SDP • For Complete Power Up/Down protection, RES/ signal is OEM Die Mfg spec. • NOTE: for normal device Operation, RES/ MUST be @ VIN > (.5V - VCC) • SDP protects during power stable and power-off to ~VCC= 2.5V • Question: Has charge pump dissipated enough or ‘logic to initiate write’ not possible thereafter? • Would have to characterize events of power-off sequences of system to validate. • OEM does not guarantee SDP can protect during Power Up/Down sequences • POWER-ON Sequence • RES/ low, VCC on, RES high 1usec after VCC @4.5V, 100usec wait til WE low. • POWER-OFF Sequence • Last write complete , RES/ low, wait 1usec, VCC off • SDP Enable tip: 4 cycle sequence does indeed write the 4th cycle data • BUT, it does NOT write the first 3 cycle sequence • SDP Disable tip: 6 cycle Data sequence is NOT written to the device • IIL(RES/ pin) = 100uA max, while IIH(RES/ pin) = 2uA. (58C1001)

  16. SDP Power Down Experiment 10/12/05 /jk

  17. Data Retention & Endurance • D/R Temp Step Reliability exercise in yr2000 for customer • 175C, 200C, 225C, 250C Temperature Steps • Based on first functional Fail encountered • Hours run til 50% devices Fail (T50) • 1.2eV Activation Energy model arrived at by customer calculation • Nullified earlier 1.6ev belief • ASI extrapolation noted at 1.3eV w/ 20yr 125C operation assumption • Hitachi 1.1eV based on Weibull plot of cumulative cell fails to 1% • Endurance Testing • 2 individual tests run with 10K cycle pre-condition followed by 1000hr L/T (15/0) • Hitachi Intrinsic Rel/Qual Data demonstrates >50K cycles (22/0) • Write Cycle related Infant Mortality • 10 , 50, 100 or 1000 cycles ??? • Enough to address ’partially’ programmed cells. • Don’t be afraid to write too much during test screening phase. 10/12/05 /jk

  18. TAA vs VCC vs Temp Shmoo’s

  19. “Weak Bit/Margin Screening” • Weak Bit/Margin test screening is standard practice in the Commercial Industry • What is Weak Bit Screening? • Goal of meeting EFR of .01-.2% on production shipments • On 5-Volt Tech, VCC can be as low as 2.5V & as high as 8.5V (VCC +/- 50% !!!) • Specific target algorithms • most often by customer application use discovery • Close Customer-Vendor Engineering coupling a Must! • Must evaluate relevance on each new technology • otherwise test time can become astronomical • Burn-in is standard Commercial industry practice on high density Memories • EFR studies in True Reliability oriented Step fashion • 100,000’s of devices used at Qual & quarterly to monthly monitoring • cell stress equality desired • High end B/I systems used, complicated timings can be achieved • Intelligent B/I monitoring functionality $$$ CAUTION: Don’t Overkill !! 10/12/05 /jk

  20. Steps to Achieving the Highest Reliable 58C1001 for Space Use Part I of II • Must be specification driven (SCD, SMD, other) • customer audits & reviews of test software & routines/limits/conditions/etc... • include golden unit correlation • creates level playing field to avoid ‘lowest bidder’ buyer determination syndrome • Must screen outside the Spec operating VCC range for key Algo’s & parameter’s • Need to fully Characterize so as to differentiate from Normal vs. Outlier distribution • Combine with Stress ‘before & after’ on key parameters. • Consider Not using Laser Repair Die for Space • 20% yield hit or build in separate groups • Inspect fuses for blown to insure no dangling shorts • Cost impact , requires higher Mag inspect • Why take chance with part that has known defect of unknown origin & effects ? • Accelerate B/I VCC !!!! • You may be better off doing 7V Vcc for 48hrs instead of 5.5V over 240hrs. Do both. • D/R verify after each of Static Bias & Dynamic Bias exercising & invert pattern for each 10/12/05 /jk

  21. Steps to Achieving the Highest Reliable 58C1001 for Space Use Part II of II “If you don’t know where you are going, you will wind up some place else” -Yogi • 100% D/R Bake Screening w/ full Array ‘0’ or 2-pass chkbd/chkbd • go as high as assembly process safely allows, typ 24 - 48hrs 150C • TOPOLOGICAL Correct Addressing !!!! • Incorporate a multitude of algorithms w/ specific address sequence’s • Row & Column Galpat, Surr Galpat, 10N march, Unique, Min Addr Ch, Row & Col Distrubs , slew, all 0/1’s, block addr change, etc…. • Perform Detailed Architecture Tutorial from actual Die deprocessing • Characterize, Characterize, Characterize • min/max VCC for each Algo/addr sequence • ICC’s esp quiescent , get outside the comfort zone. • Parameters: TAA,TACE , TWR, TOE, TWP, TDS/TDH, TBL, TAH, etc… • Reset Operation, PU & PD in general , SDP protect • Strobe & Window Compare’s • Write scenario’s • D/R failures by bit, symptom, F/A defect ID • OSCILLATING Output Syndrome Ole TI engr mgr saying: “In GOD we trust, everyone else bring data” 10/12/05 /jk

  22. Advisory Comments • WHY ship units in programmed ‘0’ state? • Not Industry std Non-Vol practice which mandates Erase state & SDP disabled • “”read-only test should be looped to minimize escape of oscillating data bit” • Do you really want to do a window compare instead on ATE • Address sequence is paramount (see earlier slides) • Structured Unique patterns & Algorithms • You’ve heard of DFT, but how bout TFD? • everything else is random ‘hope & wish’ test coverage • What about pure Galpat read address sequencing • 86min’s for 1 pass at 150ns read cycle !!! & this is just for 1 array data pattern. • Not economical during package test but food for thought’ at system test level • ASI strongly agree’s with statement on greater customer-vendor interaction on specification development at onset. 10/12/05 /jk

  23. Summary / Conclusions • More Focus on Address sequencing warranted in Test Algorithm generation. • Topological correct addressing is Paramount, everything else is Random. • Some level of Weak Bit/Margin screening is warranted , CZ needed. • Must be specification controlled. Some of customers already do. • Must avoid removing “normal distribution” die • ASI very open & willing to discuss in any detail @ your place or ours. • Would the industry be supportive of SOW to address “characterization of 58C1001 performance boundaries for mitigation of Weak cells” ? • Nasa Sponsored, w/ Industry shared results. • Thank-you for this opportunity to present in this workshop. 10/12/05 /jk

  24. Why do Business with Austin Semiconductor? • ASI only does Military Components & Services • The MIL-AeroSpace Customer is our ONLY priority • DSCC QML & Lab Suitability Certified • Standard Memory device Leader in the Military Marketplace • SRAMs, DRAMs, SDRAMs, uvEproms, FLASH, EEPROMs, VRAMs • Product Personalization to specific Customer Requirements • Source Control Drawing friendly, Audits freely welcomed • System Designer can tweak-out more performance from standard die • Custom Package requirements (ASI will even do the design work w/ package vendor) • We can make your custom product a Standard Military Drawing(SMD) • ITAR restrictions , DX/DO ratings are commonplace in factory • Renewed emphasis on New Product Development in 2005 & beyond • Customer Driven Products as opposed to technology driven 10/12/05 /jk

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