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Final FED Progress Report CMS Tracker Week 16th July 2003

Final FED Progress Report CMS Tracker Week 16th July 2003. FED FED-PMCs Status. Production of additional 40 FED-PMCs for Module Test setups. Some components were on last time buy (Xilinx 4036 FPGAs.) 40 cards have been Assembled.

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Final FED Progress Report CMS Tracker Week 16th July 2003

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  1. Final FEDProgress Report CMS Tracker Week16th July 2003

  2. FEDFED-PMCs Status • Production of additional 40FED-PMCs for Module Test setups. • Some components were on last time buy (Xilinx 4036 FPGAs.) • 40 cards have been Assembled. • 28 PMCs (passing commissioning tests) were sent to CERN this week. • Remaining cards will be sent “eventually”. • Problem: Our experienced test engineer had to leave abruptly for 6 months in the desert. The replacement engineer must share effort with work on Final FEDs. • Full updated list made of existing PMC owners, locations and status.

  3. FEDFinal FED JTAG “OptoRx” VME64x 9U board CFlash Final FEDv1 34 x FPGAs 96 channels 2 FEDs under test: ser001 at Imperial ser002 at RAL Memories Analogue Power TTC FE Unit “Primary” Side

  4. FED Project Targets • FED Project aiming to satisfy 2 targets in next 9 months: • I) FEDs for Large Scale Assembly (LSA) tests: • “September ‘03 (2?) / end ‘03 (2) / beg ‘04 (2) / mid ‘04 (6)” • 96 chan Opto FED essential • only need to provide restricted FED functionality • assumes we can use existing design FEDv1 pcbs • II) FED Pre-Production Manufacture: Q1-2/04 • to stay on final CMS installation schedule • need to demonstrate full FED functionality • assumes new design iteration FEDv2pcbs

  5. FED Status • 2 original FEDs under test since a few months: • Ser 001 is at Imperial for detailed characterisation studies of FED with Optical inputs (using Opto Test card Mk1). (see Matt Noy’s talk) • Ser 002 kept at RAL mainly for Firmware development / Electrical based / Digital tests. • A further 3 FEDs were assembled in June: • 1 with all 8 OptoRx’s • Only difference is use of XC2V1500 FE-FPGAs (cf XC2V2000 on 001 & 002) • Good news is that all 3 have just passed Boundary Scan JTAG tests. Build quality has generally been good again. Except for number of solder bridges on v. small Resistor Packs (see picture). • 50 OptoRx (new version) were sent from CERN this week.. • Almost all other components are already in hand for approx 20 FEDs. • Awaiting feedback from Atlas boards before manufacture of more PCBs.

  6. FEDFirst fully assembled board. Primary Side...

  7. FED…and Secondary Side

  8. FEDZoom in on FE Unit OpAmps Dual ADCs Delay FPGAs “OptoRx” Resistor Packs Test Connector Duplicated on Secondary Side “Primary” Side Front-End Unit = 12 channels

  9. FEDDelivery Schedule ‘03 • FEDv1 Testing is still progressing well… • No “show stoppers” as yet for using FEDv1 for Large Scale Assembly tests. • ...but quite a lot more to do. • Schedule is tight but we should be able to deliver1 FED with Firmware needed for LSA Tests by end of September (+1 FED at same time for CERN). • Software Delivery refer to Online Software Meeting/Jon Fulcher. • Then deliver further FEDv1’s according to schedule provided... “end ‘03 (2) / beg ‘04 (2) / mid ‘04 (6)” • Potential Problem: Late availability of LHC standard crates in UK. (was May but is now September?)

  10. FED Firmware and FPGAs Delay x 24 FE x 8 Now testing all 4 FPGA Final Designs together on FED... VME x 1 BE x 1 Delay FPGA: ADC Coarse and Fine Clock Skewing. FE FPGA: Scope and Frame Finding modes. BE FPGA: Event building, buffering and formatting. VME FPGA: Controls and Slow Readout path.

  11. FED Firmware Status 14th July 2003 System ACE EPROM VME FPGA Ed DAC Opto Rx EPROM Temp ADC System ACE DAC Opto Rx VME Bus Temp ADC Temp VME I2C Clocks Serial Controls Regs Clocks Serial Comms Regs Input Serial Controls VME LINK Data Data Header Mode Scope Mode Frame-Findng Mode Input Ed FIFOs DELAY FPGA x 3 x 8 Output BE FPGA Saeed Cluster Finding Mode Scope Mode Serial Comms Regs VME Link External Devices FE FPGA x 8 Ivan To be Implemented Control S-LINK S-LINK Clocks Headers Under Simulation Throttle TCS Input Under Test on FED QDR Write QDR Read TTC chanA TTCrx Data Readout Saeed, Ivan “Working” on FED Chan B QDR Controls Ed, John QDR Only for FEDv2

  12. FEDFirmware Tasks for LSA Tests • Firmware Functions now working: • Control and Readback of FE registers. TrimDACs, OptoRx etc • ADC clock skewing. • FE Scope mode data capture. • Event storage in large memory buffers. • Close to working 4-6 weeks: • Event formatting with DAQ and Tracker headers. • Readout of event data over VME. • FE APV Frame finding mode. • Still to do: • TTC clock and trigger • Buffer overflow protection • Temperature sensor control/readout

  13. FEDConclusions • FEDv1 Testing is still progressing well… • No “show stoppers” as yet for using FEDv1 for Large Scale Assembly tests. • ...but quite a lot more to do. • Schedule was always tight but we should be able to deliver1 FED with “usable” Firmware as needed for LSA Tests by end of September (+1 FED at same time for CERN test bench). • Must expect to get subsequent firmware updates (via Cflash card) in the field. • For Software delivery refer to Online Software Meeting/Jon Fulcher. • Most components in hand now, remaining including OptoRx and PCBs in hand soon... • Except late availability of LHC standard crates in UK. (was May but is now September?) • Do not foresee problems to deliver additional FEDv1’s according to schedule provided... “end ‘03 (2) / beg ‘04 (2) / mid ‘04 (6)”

  14. FEDFinal FED JTAG “OptoRx” VME64x 9U board CFlash Final FEDv1 34 x FPGAs 96 channels Memories Analogue Power TTC FE Unit “Primary” Side

  15. FED

  16. FEDLarge Scale Assembly Test Requirements 2003 • Paraphrasing from note of Piero Verdini... • “To Readout Virgin Raw Data formatted as DAQ events via VME in response to TTC trigger and clock.” • Need 96 OptoRx chans. Trigger & Readout rates are not critical. • Functionality • Does require: • Scope Mode and Software Triggers for set up. • Controls from VME for run mode, clock source, clock skew, OptoRx offsets (with readback.) • VME Event buffer with standard DAQ events. Counters for triggers & errors. • System ACE loading, Clock/Trig/Resets on TTC Chan A, Hardware throttle output. • FED delivered as a Package including Software Library to drive the Firmware. • Does not require: • S-LINK readout, Clustering mode, Spy Channel, TTC chan B, TCS (but maybe simple throttle), DAC control, pedestal/threshold data, System ACE interface, VME64x config EPROM…, VME Interrupts, Temp chip control…

  17. FEDPre-Production FEDv2 • Does require : • S-LINK readout, Clustering mode, Spy Channel, TTC chan B, TCS (but maybe simple throttle), DAC control, pedestal/threshold data, System ACE control and in situ-programming, VME64x config EPROM…, VME Interrupts, Temp chip control… • Tested with up to 20 FEDs in a crate. • All operating at target Trigger Rate of 100 kHz! • … FEDv1 has been designed for this. • Assumption: have to demonstrate full functionality before pre-production FEDv2 (Q1-2/2004.)

  18. FEDLarge Scale Assembly Setup Assumptions • Assumptions: • Use 9U VME64x crates (LHC crates available for UK tests in May.) • Clock and Trigger arrives on standard TTC Opto cable (on TTC chanA.) • Sync/Bx counters Reset by ‘101’ on chanA. • Hardware Throttle signal level on back-plane pin? • Comments: • Caution should be exercised when using a FED that may not be fully characterised to make detailed measurements of other electronics systems. • Basic FED training to be provided (in UK). • Need well defined points of contact between LSA Testers and UK. • Other FED related projects are being undertaken in UK.

  19. FED Early Electrical Data in FEDv1 sine input (1 MHz) via Cross-Point Switch test card to 12 channels Chip-Scope logic analyser capture 10 bit-raw data on 12 channels in FE FPGA ADC count preliminary first 100 (of 4k) samples @ 40 MHz

  20. FED First Optical Data in FEDv1 “APV frame” pattern on single channel Chip-Scope logic analyser capture 10 bit-raw data ADC count preliminary samples @ 40 MHz unsynchronised clocks

  21. FED Update since last Tracker Week... • 2 FEDv1 pcbs were assembled in January (without OptoRx). • Started with following preliminary tests done at RAL: • Power sequencing. • JTAG Boundary Scan (automated IC connection tests ; passed ok.) • FPGA Configuration (>30 devices) from cable and System ACE Compact-Flash card. • FE Module analogue Electrical tests using Electrical Cross-Point switch card. • (NB no VME readout yet, so data is captured in FPGA using Xilinx Chip-Scope embedded logic analysers read out via cable.) • Digital tests with simple “Test Firmware” loaded in FPGAs.

  22. CMS Tracker FED Schedule Production & Installation Design Test Pre-Pro FEDv1 (20) FEDv2 (20) FEDv3 (500) • FED x 450 installation at CERN expected to start Q3 2005

  23. FEDOverview 12 12 12 12 12 12 12 12 96 Tracker Opto Fibres CERN Opto- Rx Modularity 9U VME64x Form Factor Modularity matches Opto Links 8 x Front-End “modules” OptoRx/Digitisation/Cluster Finding Back-Endmodule / Event Builder VME module / Configuration Power module Other Interfaces: TTC : Clk / L1 / BX DAQ : Fast Readout Link TCS : Busy & Throttle VME : Control & Monitoring JTAG : Test & Configuration 9U VME64x Analogue/Digital JTAG FPGA Configuration Compact Flash FE-FPGA Cluster Finder VME Interface VME-FPGA BE-FPGA Event Builder TCS TTC TTCrx DAQ Interface Buffers Power DC-DC Temp Monitor Front-End Modules x 8 Double-sided board Xilinx Virtex-II FPGA TCS : Trigger Control System

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