Introduction to CMOS VLSI Design Lecture 11: Adders

Introduction toCMOS VLSIDesignLecture 11: Adders David Harris Harvey Mudd College Spring 2004

Outline • Single-bit Addition • Carry-Ripple Adder • Carry-Skip Adder • Carry-Lookahead Adder • Carry-Select Adder • Carry-Increment Adder • Tree Adder 11: Adders

Single-Bit Addition Half Adder Full Adder 11: Adders

PGK • For a full adder, define what happens to carries • Generate: Cout = 1 independent of C • G = • Propagate: Cout = C • P = • Kill: Cout = 0 independent of C • K = 11: Adders

PGK • For a full adder, define what happens to carries • Generate: Cout = 1 independent of C • G = A • B • Propagate: Cout = C • P = A  B • Kill: Cout = 0 independent of C • K = ~A • ~B 11: Adders

Full Adder Design I • Brute force implementation from eqns 11: Adders

Full Adder Design II • Factor S in terms of Cout S = ABC + (A + B + C)(~Cout) • Critical path is usually C to Cout in ripple adder 11: Adders

Layout • Clever layout circumvents usual line of diffusion • Use wide transistors on critical path • Eliminate output inverters 11: Adders

Full Adder Design III • Complementary Pass Transistor Logic (CPL) • Slightly faster, but more area 11: Adders

Full Adder Design IV • Dual-rail domino • Very fast, but large and power hungry • Used in very fast multipliers 11: Adders

Carry Propagate Adders • N-bit adder called CPA • Each sum bit depends on all previous carries • How do we compute all these carries quickly? 11: Adders

Carry-Ripple Adder • Simplest design: cascade full adders • Critical path goes from Cin to Cout • Design full adder to have fast carry delay 11: Adders

Inversions • Critical path passes through majority gate • Built from minority + inverter • Eliminate inverter and use inverting full adder 11: Adders

Generate / Propagate • Equations often factored into G and P • Generate and propagate for groups spanning i:j • Base case • Sum: 11: Adders

Generate / Propagate • Equations often factored into G and P • Generate and propagate for groups spanning i:j • Base case • Sum: Valency-2 equation; uses P/G of two smaller groups Gi-1:0 is simply the carry-in of this stage, ie., Ci Si = Pi xor Ci = (Ai xor Bi) xor Ci 11: Adders

PG Logic C4 = G4 + P4 G3:0 11: Adders

Carry-Ripple Revisited Note: Carry propagates through And/or network instead of MAJ gate network 11: Adders

Carry-Ripple PG Diagram 11: Adders

Carry-Ripple PG Diagram 1-bit prop/gen cell delay of And/OR in grey cell Final SUM bit xor 11: Adders

PG Diagram Notation Generate only Both Gen/Prop 11: Adders

Carry-Skip Adder • Carry-ripple is slow through all N stages • Carry-skip allows carry to skip over groups of n bits • Decision based on n-bit propagate signal Critical path: Generate carry in first bit, then ripple thru next three bits. Then skip next two four-bit stages, then ripple through last stage. 11: Adders

Carry-Skip PG Diagram For k n-bit groups (N = nk) 11: Adders

Carry-Skip PG Diagram For k n-bit groups (N = nk) First, last group ripple skip thru muxes 11: Adders

Variable Group Size Delay grows as O(sqrt(N)) Smaller groups at first/last 11: Adders

Carry-Lookahead Adder • Carry-lookahead adder computes Gi:0 for many bits in parallel. • Uses higher-valency cells with more than two inputs. 11: Adders

CLA PG Diagram Collecting Generate/Propagate over many cells 11: Adders

Higher-Valency Cells Just the recursive definition of Generate 11: Adders

Carry-Select Adder • Trick for critical paths dependent on late input X • Precompute two possible outputs for X = 0, 1 • Select proper output when X arrives • Carry-select adder precomputes n-bit sums • For both possible carries into n-bit group 11: Adders

Carry Select Critical Path N = adder size in each group, K groups Tselect = Tpg + [N+(K-2)]TAO + Tmux Slightly faster than Carry-skip. For optimal delay, do not want each group to have the same size, want each group to grow in order to match mux select arrival time with carry generation time. 11: Adders

Carry-Increment Adder • Factor initial PG and final XOR out of carry-select 11: Adders

Carry-Increment Adder • Factor initial PG and final XOR out of carry-select Adders in Carry-select have redundant logic, factor this out, reduces logic size, delay essentially the same. 11: Adders

Variable Group Size • Also buffer noncritical signals Observe that buffer is added so that buffer delay is not on critical path! 11: Adders

Tree Adder • If lookahead is good, lookahead across lookahead! • Recursive lookahead gives O(log N) delay • Many variations on tree adders 11: Adders

Buffers not really necessary Lots of logic levels! Brent-Kung 11: Adders

High Fanout Sklansky 11: Adders

Lots-o-wires Kogge-Stone 11: Adders

Tree Adder Taxonomy • Ideal N-bit tree adder would have • L = log N logic levels • Fanout never exceeding 2 • No more than one wiring track between levels • Describe adder with 3-D taxonomy (l, f, t) • Logic levels: L + l • Fanout: 2f + 1 • Wiring tracks: 2t • Known tree adders sit on plane defined by l + f + t = L-1 11: Adders

Tree Adder Taxonomy 11: Adders

Tree Adder Taxonomy Logic levels Fanout Wire tracks 11: Adders

Han-Carlson 11: Adders

Knowles [2, 1, 1, 1] Half the wires at last stage than Kogge-Stone, but double the loading. 11: Adders

Ladner-Fischer 11: Adders

Taxonomy Revisited 11: Adders

Hybrid Tree/Carry Select • Hybrid adders use tree-logic to compute the carries, but also use short ripple chains to reduce the number of gates • Fig 10.39 of the book shows a good example of a sparse tree adder 11: Adders

Summary Adder architectures offer area / power / delay tradeoffs. Choose the best one for your application. 11: Adders

Introduction to CMOS VLSI Design Lecture 11: Adders