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EE573 VLSI 시스템개론

EE573 VLSI 시스템개론. 2004 년도 봄 학기 경 종민. 강의 정보. 목적 ; 경쟁력 있는 ( 시스템 개념 , know-what 과 시장을 아는 기술자 , 생각하고 질문하고 표현할 줄 아는 ) SoC 설계자로 전향케 함 . 장소 ; LG MM-> 창의학습관 201 호 (?) 조교 ; 심희준 , 김형옥

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EE573 VLSI 시스템개론

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  1. EE573 VLSI 시스템개론 2004 년도 봄 학기 경 종민

  2. 강의 정보 • 목적; 경쟁력 있는 (시스템 개념, know-what 과 시장을 아는 기술자, 생각하고 질문하고 표현할 줄 아는) SoC 설계자로 전향케 함. • 장소; LG MM-> 창의학습관 201 호(?) • 조교; 심희준, 김형옥 • Website ; Q&A(조교, 교수), 숙제 및 모든 제출물, 수강생 개인 사진+소개 자료 제출 요망(1주 내로)(http://vswww.kaist.ac.kr/course/ee573/) • Text ; 따로 없음 • Reference ; 추후 통지

  3. EE573 강의 내용과 일정 • (1; 3/3) IT Future Trend and Role of SoC VLSI • (1; 3/8) Various SoC-Related Applications, Business Models, Global Industries & Career/Life Planning • (3; 3/10,15,17) Key Issues in Embedded System Design (Requirement Generation & HW/SW Co-Design and Co-Verification) • (3; 3/22,24,29) High-Speed Design Techniques • (0.5; 3/31) 45-min.Test(Mid-term) • (1.5; 3/31,4/7) Signal Integrity Issues • (3; 4/12,14,19) Infrastructures (Power/Ground & Clocks), Interconnections and Packaging Techniques • (1; 4/21) IP-Based Design Methodology • (1; 4/26) How to present, write, talk, discuss, negotiate and live successful life • (1; 4/28) Testing, Reliability and Manufacturing Issues • (1; 5/3) Reconfigurable Systems Design Techniques • (1; 5/10, 7:30 am-10:30 am) Poster Presentation • (2.5; 5/11,17,19) Low-Power Design Techniques • (0.5; 5/19) 45-min Test (Final Exam) • (2; 5/24, 6/2) Memory System Design Techniques • (2; 6/14, 6/16, 7:30 am-10:30 am) Oral Presentation (15 min. for each person) Total 27 units

  4. 강의 내용과 일정 • (No. of units ; Date) Subject of Learning • (1; 3/3) IT Future Trend and Role of SoC VLSI • (1; 3/8) Various SoC-Related Applications, Business Models, Global Industries & Career/Life Planning • (3; 3/10,15,17) Key Issues in Embedded System Design (Requirement Generation & HW/SW Co-Design and Co-Verification) • (3; 3/22,24,29) High-Speed Design Techniques • (0.5; 3/31) 45-min.Test(Mid-term) • (1.5; 3/31,4/7) Signal Integrity Issues • (3; 4/12,14,19) Infrastructures (Power/Ground & Clocks), Interconnections and Packaging Techniques • (1; 4/21) IP-Based Design Methodology

  5. 강의 내용과 일정 • (1; 4/26) How to present, write, talk, discuss, negotiate and live successful life • (1; 4/28) Testing, Reliability and Manufacturing Issues • (1; 5/3) Reconfigurable Systems Design Techniques • (1; 5/10, 7:30 am-10:30 am) Poster Presentation • (2.5; 5/11,17,19) Low-Power Design Techniques • (0.5; 5/19) 45-min Test (Final Exam) • (2; 5/24, 6/2) Memory System Design Techniques • (2; 6/14, 6/16, 7:30 am-10:30 am) Oral Presentation (15 min. for each person) • Total 27 units

  6. Grading System • Homework ; ~5 pieces (20%) • 출석 ; n 번째 결석시 (n-2)% 씩 감점 • Midterm ; 15% • Final ; 15% • Poster(10%) + Presentation(10%) ; 20% • Oral Presentation(15%) + Written Paper (15%) ; 30%

  7. IT Future Trend and Role of SoC VLSI 3/3 (#1)

  8. What is SoC?? • Printed Circuit Board vs. Silicon board • Design Reuse  Use IP !! • Design Specification  Use C Language !! • Verification Methodology  In-System Verification !! RTL P Netlist ROM vs.

  9. PCS PCs Color TV Cable TV Cellular VCRs DVB Black & White TV DVD 1 million Units 15 5 10 20 years Advent of SOC • Growing design productivity gap between gate density (58%/Y) and designer productivity (21%/Y) • Shrinking Time-To-Market (narrow market window) • Viable solution  Design Reuse International Technology Roadmap For Semiconductors 1999 Ed. - Semiconductor Industry Association Wireless Communications Report, BIS, Boston, 1995+ Dataquest

  10. Evolution of reuse Until early 80’s TTL/MSI Reuse of Tr. 80’s-90’s ASIC/ASSP Reuse of Gates Late 90’s – System-on-chip Reuse of Socketized IP Hard component from A company Virtual component from C company Hard component from B company Virtual component from D company

  11. uP Core SRAM FLASH uP Core SRAM D-Cache USB FLASH Logic MPEG FIFO SRAM Logic SW I/F IP Design methodology & reuse model Plug & play SOC Complex ASIC with a few IPs ASIC on DSM Logic Area Driven Timing-driven design (TDD) Block-based design (BBD) Platform-based design (PBD) Personal Reuse Designer-specific reuse practices Retaining key personnel Source Reuse Functional starting points for block design Document, testbench, predictability Core Reuse Predictable, Pre-verified, Core function Firm/hard IP Virtual Component Reuse Socketized Functions for Plug & Play integration Opportunistic IP Reuse Planned IP Reuse Adopted from ‘Surviving the SOC revolution’ by H. Chang et.al.

  12. Mote

  13. Artist's conception of future MFI with optical flow sensors and radio. (Quan Gan, UC Berkeley, March 2004)

  14. Homework #1 (Smart Dust by Pister); Read the following thesis and comment. (due 2 weeks; 3/17 class) • http://www-bsac.eecs.berkeley.edu/archive/users/hollar-seth/publications/cotsdust.pdf

  15. Composition of TWG (2003)

  16. Future Prospect of IC Technology (ITRS) 2002. 9.9

  17. Contents • Introduction • ITRS • Overall Roadmap • Product Generation • Lithography • Package • Power • Cost • Design Technology Challenges • Introduction • Complexity, Methodology • Design Technology Challenges

  18. 1992NTRS 2001ITRS 2000update 1994NTRS 1999ITRS 1997NTRS 1998Update SIA ITRS Introduction • ITRS International Technology Roadmap for Semiconductors • Predicts the main trends in the semiconductor industry • Provides a reference of requirements, potential solutions, and their timing for the semiconductor industry • ITWG (International Technology Working Group) http://public.itrs.net

  19. ITWG • Overall Cordination • ORTC(Overall Roadmap Technology Characteristic) • System Driver • Focus ITWGs • Design • Test • Process Integration, Device, and Structures • Front End Process • Lithography • Interconnection • Factory Integration • Assembly and Packaging • Crosscut ITWGs • Environment, Safety, and health • Yield Enhancement • Metrology • Modeling and Simulation

  20. Prediction Classification • Red Brick Wall • There are no “known manufacturable solution” to continued scaling • Historical trends of progress might end if some real breakthroughs are not achieved in the future • Yellow: defined as “manufacturable solutions are known” • White: defined as manufacturable solution are known and are being optimized

  21. ITRS2001 • ITRS(2001) • Reports Improvement Trends • Integration Level (Moore’s Law), Cost, Speed, Power, Compactness, Functionality • Provides 15-years outlook on the major trends Each technology written by corresponding ITWG (International Technology Working Group) Composition of the ITWG < By Regions > < By Affiliations >

  22. ITRS2001 “Production” time (year of production) • When the first company brings a technology to production and a second company follows within three months < Production Ramp-up Model and Technology Node >

  23. Product Generation • Product Generations & Chip-Size Model • DRAM (Historically recognized as the technology drivers for the entire semiconductor industry) • Minimization of the area occupied by the memory cell • Maximization of the capacitance for charge storage • MPU/ASIC • Length of the transistor gate • Number of interconnect layers • Metal half-pitch will trail slightly behind or equal to the DRAM half-pitch • DRAM and microprocessor products will share the technology leadership role

  24. Product Generation • Product Generations & Chip-Size Model

  25. Product Generation • Product Generations & Chip-Size Model

  26. Lithography • To maintain historical trend (Reducing cost/function by 25~30%/year) • Enhance equipment productivity • Increase manufacturing yields • Use the largest wafer size available • Increase the number of chips available on a wafer

  27. Package • Number of Pads and Pins • Increase number of I/O signals • For higher number of functions on a single chip • Additional power and ground connections To optimize power management To increase noise immunity • MPU (1:2 = I/O : power/ground) • Two power/ground pads for every signal I/O pad • ASIC (1:1) • One power/ground pad for every signal I/O pad

  28. Package • Number of Pads and Pins

  29. Package • Pin count/Cost-per-pin # of package pin/balls increases at 10%/year Cost/pin decreases at 5%/year • Average cost of packaging will increase at 5%/years • To reduce the overall system pin requirements • Combining functionality into SOC • Multi-chip modules • Bumped chip-on-board

  30. Package • Pin count/Cost-per-pin

  31. Package • Electrical Signals Instructions/second doubles every 1.5~2 years Increase Processing power • To optimize signal and power distribution • Increasing # of layers of interconnect • Size downscaling of interconnect • Using copper(low resistivity) • Using inter-metal insulating materials of lower dielectric constant

  32. Power • Reduction of power supply voltage • Reduction of power dissipation • Reduction of transistor channel length • Reduction of reliability of gate dielectrics

  33. Cost • Reducing cost per function by 25~30%/year • Twice the functionality on-chip every 1.5~2 years

  34. DT Introduction • DT • Enables the conception, implementation, and validation of microelectronics-based systems. • Include tools, libraries, manufacturing process characterization, and methodologies • Area • Design Process • System-Level Design • Logical/Circuit/Physical Design • Design Verification • Design Test • Crosscutting Challenges • Productivity • Power • Manufacturing Integration • Interference • Error-Tolerance

  35. Design Productivity Gap # of available transistors grows faster than the ability to design them meaningfully Investment in process technology has by far dominated investment in design technology • Software now routinely accounts for 80% of embedded systems development cost • Verification engineers are twice as numerous as design engineers on microprocessor project team • Test cost has grown exponentially relative to manufacturing cost

  36. Design Productivity Gap

  37. DT Complexity • Silicon Complexity • Non-ideal scaling of device parasitics and supply/threshold voltages • Leakage, power management, circuit/device innovation, current delivery • Coupled high-frequency device and interconnect • Noise/interference, signal integrity analysis and management, substrate coupling, delay variation due to cross-coupling • Manufacturing equipment • Statistical process modeling, library characterization • Scaling of global interconnect performance relative to device performance • Communication, synchronization

  38. DT Complexity 5. Decreased reliability • Gate insulator tunneling and breakdown integrity, joule heating and electromigration, single-event upset, general fault-tolerance 6. Complexity of manufacturing handoff • Reticle enhancement and mask writing/inspection flow, NRE cost 7. Process variability • Library characterization, analog and digital circuit performance, error-tolerant design, layout, reuse, reliable and predictable implementation platforms

  39. DT Complexity • System Complexity • Reuse • Support for hierarchical design, heterogeneous SOC integration (modeling, simulation, verification, test of component blocks) especially for analog/mixed-signal • Verification and test • Specification capture, design for verifiability, verification reuse for heterogeneous SOC, system-level and software verification, verification of analog/mixed-signal and novel devices, self-test, intelligent noise/delay fault testing, tester timing limits, test reuse • Cost-driven design optimization • Manufacturing cost modeling and analysis, quality metrics, co-optimization at die-package-system levels, optimization with respect to multiple system objectives such as fault tolerance, testability, etc.

  40. DT Complexity 4. Embedded software design • Predictable platform-based system design methodologies, co-design with hardware and for networked system environments, software verification/analysis 5. Reliable implementation platform • Predictable chip implementation into multiple circuit fabrics, higher-level handoff to implementation 6. Design process management • Design team size and geographic distribution, data management, collaborative design support, “design through system” supply chain management, metrics and continuous process improvement

  41. DT Methodology Precepts • Design Methodology combines • Top-down planning and search (system specification and constraints) with • Bottom-up propagation (physical laws, limits of manufacturing technology/cost)

  42. DT Methodology Precepts • Future Design Methodologies and component tools • Exploit reuse • Evolve rapidly( evolution of suite vectors from simulation to verification, constraints for synthesis and optimization, and test) • Avoid iteration • Replace verification by prevention(ex; lower-level problems, i.e., crosstalk/delay uncertainty, can be better addressed by upper-level prevention, i.e., shielding/repeater insertion)

  43. DT Methodology Precepts • Improve predictability • Orthogonalize concerns; divide and conquer, treat separately if possible(computing and communication, behavior and architecture, etc.) • Expand scope; gather and conquer, treat together if possible(digital and analog, digital HW and software, internal,, operation and human interface, multi-level modelling, simulation) • Unify; synthesis and analysis, logical/physical/timing, design and test.

  44. DT Methodology • Methodology Precepts

  45. Design Technology • DT Area • Design Process • System-Level Design • Logical, Circuit, and Physical Design • Design Verification • Design Test

  46. Design Technology

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