SLHC Meeting CERN, 21 May 2008

1. Global Triggers, TCA Technology M. Stettler, M. Hansen (CERN) C. Foudas, G. Iles (Imperial College) J. Jones (Princeton) A. Taurok, H. Bergauer, C.-E. Wulz (Vienna) Presented by C.-E. Wulz SLHC Meeting CERN, 21 May 2008

2. COND  ALGO COND  ALGO Sync delay PSB REC Sync delay SYNC Global Trigger Concepts for LHC and SLHC LHC GTL FDL Sync delay GMT 128 Algo GTL Final OR GCT Sync delay PSB Prescalers & Trigger Counters Technical Triggers Totem, Castor, ZDC, BTPX, BSC, … SLHC COND chip Optical links FDL chip Sync delay GMT FPGA: Standard Conditions GTL nn Algo (and, or, not) Sync delay GCT COND chip Final OR - FPGA: DSPs (XC5V100T) - FPOA: DSP array Tracker Trigger Sync delay Tracker ‘Conditions’ Prescalers & Trigger Counters ‘Conditions’ Totem, Castor, ZDC, BTPX, BSC, …

3. Synchronize all Trigger Objects to arrive at the same time at the logic chip 2008 Version: Muons: done by GMT; Calo_objects: done by PSB; Technical Triggers: done by PSB SLHC Version: Muons: done by GMT; Calo_objects:done by GCT; TechTrig: done by SYNC chip Tracker: done by Tracker_Trigger Send all Trigger Objects into one chip to be able to make any correlations between them Use an FPGA to change trigger conditions as required by physics New trigger setup: -> configure FPGA with new trigger conditions New parameter values for same setup: 2008 Version: Load new ET and pT thresholds by software SLHC Version: Load all values by software ( Upgrade Version) Calculate physics trigger algorithms in parallel (FPGA branch) 2008 Version: 128 Algorithms, limited by board layout, connectors and chip size SLHC Version: Extend to ‘nn’ Algorithms <- ‘Algo’ signals inside chip (chip size will be the only restriction) Final OR mask for all Algorithm bits; Prescaler & Counter for each Algorithm SLHC: maybe more requirements SLHC Version: Array of DSPs for complex physics triggers C++ code -> trigger program with constant latency(!) Each trigger object is received twice, on 2 optical links Global Trigger Concepts for LHC and SLHC

4. Input to Global Trigger • Global Calorimeter Trigger (GCT): redefinition (reduction?) of trigger data • 4 e/, 4 isolatetd e/(ET, h, f) 4 e/ with ISOLATION bit • 4 central jets, 4 forward jets(ET, h, f)  n jets • 4 tau jets • total_ET, HT  apply set of thresholds in GCT • and send resulting bits to FDL chip • missing_ET(ET, f) • “jet counts” (now towers above thr., ring ET’s) • More than 4 objects per type: 5 or 6 (?)  Simulation for SLHC • Global Muon Trigger (GMT): • 4 muons (pT, h, f, mip, iso, charge, quality) • Tracker Trigger: • Tracks/jets with h and f COND chips • ‘Conditions’ calculated in Tracker Trigger  FDL chip

5. Single particle thr1, h, f window1 ieg1 ieg1 Single particle thr1, h, f window1 ieg2 ieg2 Single particle thr1, h, f window1 ieg3 ieg3 Single particle thr1, h, f window1 ieg4 ieg4 Single particle thr2, h, f window2 Single particle thr2, h, f window2 Single particle thr2, h, f window2 Single particle thr2, h, f window2 CMS GT Standard Algorithm in FPGA: Example Standard CONDITION chip Predefined VHDL code Missing Energy TEMPLATE ieg1 ieg3 Dh, Df Correlation TEMPLATE ieg2 ieg4 Single particle TEMPLATE Dh, Df Correlation ET thresholds 1,2 h, f window 1,2 Parameters Find 2 out of 4 particles fulfilling all conditions Missing Energy threshold IEG condition: ieg2wsc Missing ET condition: MET FDL chip Mask, Veto_mask Combinatorial logic: Algorithm = ieg2wsc and MET Final_OR ALGO bit (i) prescalers

6. Condition chip with DSP array or RISCs Trigger objects (GCT, GMT, TrackerTr…) Parameters Hardwired logic* DSP Condition program Latency = # of instructions XC5VFX100T: 256 DSP48E(550MHz), 4 Ethernet MAC, 3 PCIexpress end points, 16 GTX RocketIO (6.5Gb/s) 680 IO (1.25Gb/s LVDS) Condition bit *) if DSPs are implemented in FPGA • Constraints: • # of Conditions  # of DSPs • # of instructions  latency limit • Keep pipeline structure Parallel or tree structures Trigger objects Trigger objects DSP DSP DSP DSP DSP DSP Latency Latency DSP OR Condition bit Condition bit  Algorithm logic in FDL chip  Algorithmlogic in FDL chip

7. Spy_mem‘s & Ringbuffers Spy_mem‘s & Ringbuffers Control CPU Control CPU Event builder LVDS LVDS LVDS LVDS LVDS Prescalers Trigger Counters Global Trigger board for SLHC Ethernet IP DAQ chip Ethernet IO CMS - DAQ Preliminary! 2 sets of opt. rcvers Ethernet IP L1A_daq + Serial TX L1A_daq + Serial TX RX: Serial parallel COND_logic or DSP array nn Algo (and, or, not) LVDS Final OR Condition bits GCT: 5 ... GMT: 2 Tracker: ~2 .. COND chip Parallel data Sync circuits Condition bits FDL chip Ethernet IP TIMING circuits CLK, BCRES, ... CLK, BCRES, .. SYNC Chip Ethernet IP

8. Trigger system design based on Telcom developments

9. ATCA standard

10. ATCA connectivity

11. TCA

12. Data processing TCA module + custom active switching backplane Data processor card schematics have been designed (M. Stettler) and parts have been bought. The card is under layout at Los Alamos. Advanced PCB manufacturing techniques (e.g. micro-vias that penetrate several layers) are needed. Board stackup has been completed and verified with vendor. The Backplane has been designed (J. Jones + M. Stettler) but will be tested after the processor card. A TCA crate and a commercial backplane have been bought and are already at CERN. The first prototypes are expected to arrive at CERN in Summer 2008. TCA for GCT Quiet/ MIP Bits

13. Main QM Data Processing Module • Receives and transmits data via front panel optical links. • On board 72x72 Cross-Point Switch allows for dynamical routing of the data either • to a V5 FPGA or directly to the uTCA backplane. • The module can exchange data with other modules either via the backplane or via the • front panel optical links.

14. Custom TCA Backplane • Instrumented with 144x144 cross-point switch for extra algorithm flexibility. • Allows dynamical or static routing of the data to different Data Processing Modules.

15. Routing detail

16. BACKUP

17. Backplane 6 7 8 9 1 2 3 4 5 10 11 12 13 14 15 16 17 18 19 20 21 CAEN VME CONTROLLER PSB PSB PSB PSB PSB PSB PSB FREE VME FREE VME L1A_OUT L1A_OUT TCS spare TIM GTFE GMT FDL GTL 128 Algo L1A TOTEM 8 RPC muons 4 DT muons 4 CSC muons CLK, ORBIT 4TAU-JET, ET*, JetNr, 4IEG, 4EG, 4JET, 4fJET PC: RUN Control (ET*=total ET, HT, MET) MIP/QUIET bits Detector subsystems TECHNICAL TRIGGER SIGNALS TTC - GPS-TIME S-links: DAQ, EVM aTTS DAQ APV-EMULATORS STATUS SIGNALS Global Trigger Crate 2008

18. I/O, Hardware I/O requirements: 4 calo objects(jet, ieg,..)  64 bits/40MHz  2.56 Gbps 4 calo objects(jet, ieg,..)  64 bits/80MHz  5.12 Gbps 1.25 Gbps LVDS IO for each pin pair:  31 bits/40MHz // 15 bits/80MHz Virtex5 XC5VFX100T: 256 DSP48E(550MHz), 4 Ethernet MAC, 3 PCIexpress end points, 16 GTX RocketIO (6.5Gb/s) 680 =340 pairs IO (1.25Gb/s LVDS) • DSP48E Slices : • add/subtract o = Z ± (X + Y +CIN) • Accumulate o = o + A&B + C //concatenate • Accumulate & shift • Multiply Accumulate(MACC) • MUX, BarrelShifter, Counter, multiply, divide, • square_root, square_root of sum of squares, • Parallel FIR Filters,… • Altera Stratix III • EP3SE110: for DSP+Memory applications • DSP: 448 18x18 Multipliers for 550 MHzclock • 896 18x18 sum_of_multipliers • 56(88) LVDS 1.25Gb/s with serializer/deserializer (SERDES) • programmable pre-emphasis, (RapidIO, … ) • 64(96) LVDS low speed • DSP block : • 300 MHz; • 8 mult18x18, regs, adders, • subtractors, accumulators, multiplexer, … FPOA (..object arrays) 1GHz clock 256 ALU Arithmetic Logic Units 16 bit 64 MAC multiply&accumulate units 80 RF register set( 64 regs 16 bit) 2 fast serial IO links