Hysteresis Analysis

1. Hysteresis Analysis SW2140 MTJ

2. Wafer Layout Red dies are measured e3 is also measured at Hitachi Yes Yes Yes Yes Yes Yes Annealing Direction Yes Yes Yes Yes e3 Yes Yes Yes Yes g3 h3 Only chips labeled “Yes” were exposed in the e-beam tool. Unshaded chips should all be open devices, i.e. nearly infinite resistance.

3. Device Matrix Row x (nm) y(nm) Shape Hitachi label(col. #) A 60 4000 TEM test site 1 B 40 80 Ellipse 2 C 40 100 Ellipse 3 D 40 120 Ellipse 4 E 50 100 Rectangle 5 F 50 100 Ellipse 6 G 50 100 Hexagon 7 H 50 150 Rectangle 8 I 50 150 Ellipse 9 J 50 150 Hexagon 10 K 60 120 Rectangle 11 L 60 120 Ellipse 12 M 60 120 Hexagon 13 N 60 180 Rectangle 14 O 60 180 Ellipse 15 P 60 180 Hexagon 16 Q 80 160 Rectangle 17 R 80 160 Ellipse 18 S 80 160 Hexagon 19 T 80 240 Ellipse 20 U 80 240 Hexagon 21 Our col. # runs from 1 to 30, the same as Hitachi row #. Column 1 is TEM test sample

4. MR ~ area

5. Col.# ~ MR

6. Hc ~ area