1. FPGA_Editor Probes

2. Adding a Probe : GUI • Probes tie an internal signal to an output pin • To Launch the GUI: • Click the “probes” button on the Push Button Panel • Tools Probes • Probes can be added, deleted, edited, or highlighted .

3. Adding a Probe : GUI • Click the add button • Opens the define Probe window • Select desired probes to Delete, Edit, or Hilite • After a Probe has been added: • Click Bitgen to create a new bitfile • Click Download to open iMPACT programmer • Edit the script file and add comments to document any changes .

4. Creating a Probe • Enter a Pin Name • Filter feature to limit net options • Select Net to be probed • Method • Automatic routing • Selects the shortest route to closest pin • Possible long wait times • Manual routing • Specific pins can be selected • Selects the shortest route if multiple pins are selected • Click OK .

5. Probe Script File Syntax • probe (script begin) • probe ([-pinname <pinName>] [-targetpins <pinNumber> [-usedpin <pinNumber>] [-noroute] add [<netName>]) • probe ([-pinname] change <net_or_PinName> <attrName> <attrValue> ) • probe ([-pinname] route <netOrPinName>) • probe ([-all] route) • probe ([-pinname] unroute (<netOrPinName>) • probe ([-all] unroute) • probe ([-pinname] delete <netOrPinName>) • probe ([-all] delete) • probe ([-pinname] list <netOrPinname>) • probe ([-all] list) • probe save (<probeScriptFile>) • probe (script end) .

6. Example FPGA Editor Probe Script File • Manually create a script file to be run from FPGA Editor. The probe commands and targetpinsare case sensitive, net names and pinnames are not probe script begin save design ddr_probe1.ncd probe add “Net1” –pinname tstpoint1 –targetpins M1 M2 –usedpin M1 probe -all list probe save ddr_probe1.scr save -w design ddr_probe1.ncd probe script end • Save the design at the beginning and end of the script file • Do not use a –w for the 1st save to avoid overwrite an existing NCD file • The last save should overwrite the 1st save using the –w switch • List all of the probes to verify they were implemented correctly • Save the probe file with same name as the NCD file .

7. Example DOS Probe Script File • Create a script file to be run using fpga_edline from DOS probe script begin save design ddr_probe1.ncd setattr main edit-mode toggle probe add “N123” –pinname tstpoint1 –targetpins M1 M2 –usedpin M1 probe -all list probe save ddr_probe1.scr save -w design ddr_probe1.ncd probe script end • This is the same probe file that is run from the GUIs except add a line to place fpga_edline into the read/write mode • At the DOS prompt type: fpga_edline <file.ncd> -p <probe_file.scr> .

8. Running the Probe Script • Run the script file from the GUI • Press the probes button , then press Open Probes… • From the menu Tools  Probe…, then press Open Probes… • Type post probes at the command line, then press Open Probes… • Run the script using Tool Scripts Playback… , then browse to the <filename>.scr file • Use the FPGA Editor command line to create probes • Sometimes it is easier to find the net, that needs to be probed, by navigating through the design using the array window. Once the desired net is found, the probe command can be manually entered using the command line • The lab will demonstrate examples of entering probes using the command line .

9. Add a Component • Configure the Block before pins are added • Select an unused Block (CLB, IOB, …) and press the Add button • If Automatic Post is selected in the Main Properties box, a properties dialogue box will open • If Automatic Post has not been selected then select the component and press the Attribute Button to open the dialogue box • Type the name that you want assigned to the component in the Name box • Select the Type • CLB select either SliceL or SliceM (Spartan3 and Virtex4) • SliceL is Logic Only • SliceM is for Memory such as an SRL or RAM • IOB V2 and V2PRO select either IOB(single ended) or DIFFM or DIFFS • 7.1 IOBs default to a Differential IO standard • IOB V4 select either IOB (single ended), IOBS or IOBM • 7.1 IOBs default to a Differential IO standard • Press the Apply button. .

10. Edit a Component • Double click the left mouse button on the component to open the Block window or select the component and press the Edit Block button • If the selected component appears muted (Grayed out) in the Block window then press the Begin Editing toolbar button • If this button is disabled, check to make sure the edit mode for your design is set to Read Write • Look-up tables (LUT) and flip-flops have several check boxes associated with them • Carry mode can be specified by selecting the appropriate check box • Multiplexer (MUX) symbols have triangular input pins. Click on the appropriate pin to highlight the path through that pin • LUT equations are modified by using attributes for the component • In the Block window, click on the Show/Hide Attributes (F=, G=) toolbar button • Equations are a boolean representation of the logic .

11. LUT Equation • The following are valid symbol definitions. Symbol Logical Gate ~ NOT + OR * AND @ XOR • Both the Geqn and Feqn map the A4 to the G4, A3 to the G3 and so on. • A valid equation for the Geqn could be (~(a1*~a2)+(a3@~a4) • A valid equation for the Feqn could also be (~(a1*~a2)+(a3@~a4) • Once the equations are entered, press the apply button. • DRC is run on the equation. Fix any errors and make sure you understand any warnings • Valid warnings may be dangling input or output pins, if nets have not been added to the Slice yet .