ECE 331 – Digital System Design

1. ECE 331 – Digital System Design Single-bit Adder Circuits (Lecture #11)

2. ECE 331 - Digital System Design The Half Adder (HA) Single-bit Adder Circuits

3. ECE 331 - Digital System Design Binary Addition 0 0 1 1 + 0 + 1 + 0 + 1 0 1 1 10 Sum Carry Sum

4. ECE 331 - Digital System Design The Half Adder Sum = A'.B + A.B' = A xor B Carry = A.B

5. ECE 331 - Digital System Design The Half Adder A Sum B Sum A HA B Carry Carry (c) Circuit (d) Graphical symbol

6. ECE 331 - Digital System Design The Half Adder in VHDL LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY halfadd IS PORT ( A, B : IN STD_LOGIC ; Sum, Cout : OUT STD_LOGIC ) ; END halfadd ; ARCHITECTURE LogicFunc OF halfadd IS BEGIN Sum<= A XOR B; Cout <= A AND B; END LogicFunc ; Filename: halfadd.vhdl Contains both the entity and the architecture statements

7. ECE 331 - Digital System Design The Full Adder (FA) Single-bit Adder Circuits

8. ECE 331 - Digital System Design Binary Addition 0 0 0 0 0 0 1 1 + 0 + 1 + 0 + 1 0 1 1 10 Carry-in 1 1 1 1 0 0 1 1 + 0 + 1 + 0 + 1 1 10 10 11 Carry-out Sum

9. ECE 331 - Digital System Design The Full Adder

10. ECE 331 - Digital System Design The Full Adder A B Cin 00 01 11 10 1 1 0 1 1 1 Sum = A xor B xor Cin Cout = A.B + A.Cin + B.Cin Sum Cout A B Cin 00 01 11 10 1 0 1 1 1 1

11. ECE 331 - Digital System Design The Full Adder A B Sum Cin Cout

12. ECE 331 - Digital System Design The Full Adder in VHDL LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fulladd IS PORT ( Cin, A, B : IN STD_LOGIC ; Sum, Cout : OUT STD_LOGIC ) ; END fulladd ; ARCHITECTURE LogicFunc OF fulladd IS BEGIN Sum<= A XOR B XOR Cin ; Cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ; END LogicFunc ;

13. ECE 331 - Digital System Design The Full Adder s Sum Cin HA c s B Cout HA c A (a) Block diagram Cin Sum B A Cout Half Adder Half Adder (b) Detailed diagram

14. ECE 331 - Digital System Design The Full Adder in VHDL Construct Full Adder from two Half Adders Use Structural VHDL Realize using hierarchical design Design half adder Interconnect half adders Include any additional logic

15. ECE 331 - Digital System Design VHDL: Components Specify the logical sub-circuits (i.e. components) that will be used in the hierarchical design. Define the interface to the sub-circuit. Uses the same format as the Entity Statement. Sub-circuits are interconnected using “wires”. This is known as Structural VHDL. The architecture statement for the sub-circuit may be included in the same file as the upper level design or in a separate file. If included in a separate file, it must be compiled prior to compilation of the upper level design.

16. ECE 331 - Digital System Design VHDL: Components Component Statement COMPONENT <component name> PORT ( <interface signals> : mode type) ; END COMPONENT ; • Component Instantiation named association <instance name> : <component name> PORT MAP ( <component port names> => <signal names>) ; <instance name> : <component name> PORT MAP ( <signal names> ) ; positional association

17. ECE 331 - Digital System Design The Full Adder in VHDL Cin Sum B A Cout Half Adder Half Adder ports ports LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fulladd IS PORT ( Cin, A, B : IN STD_LOGIC ; Sum, Cout : OUT STD_LOGIC ) ; END fulladd ;

18. The Full Adder in VHDL Cin Sum B A Cout Half Adder Half Adder signal signals ARCHITECTURE Structure OF fulladd IS SIGNAL s1, c1, c2: STD_LOGIC ; COMPONENT halfadd PORT ( A, B : IN STD_LOGIC ; Sum, Cout : OUT STD_LOGIC ) ; END COMPONENT ; BEGIN ha1 : halfadd PORT MAP ( A => A, B => B, Sum => s1, Cout => c1 ) ; ha2 : halfadd PORT MAP ( A, B, Sum, c2 ); Cout <= c1 OR c2 ; END Structure ; component declaration named association component instantiation positional association

19. ECE 331 - Digital System Design VHDL: Packages Packages (and libraries) allow frequently used functions and components to be “centrally” located. Component declarations are included in package files rather than in the VHDL code for the hierarchical design. The associated VHDL models for the components are included in separate files. The compiled VHDL models are typically included in the same library. When the package file is compiled, the package is created and stored in the working directory.

20. ECE 331 - Digital System Design VHDL: Packages Package Declaration LIBRARY ieee ; USE ieee.std_logic_1164.all ; PACKAGE <package name> IS <package declarations> ; END <package name> ; • Package Declaration LIBRARY work ; USE work.<package name>.all ;

21. ECE 331 - Digital System Design The Full Adder in VHDL (The Package File) LIBRARY ieee ; USE ieee.std_logic_1164.all ; PACKAGE halfadd_package IS COMPONENT halfadd PORT ( A, B: IN STD_LOGIC ; Sum, Cout: OUT STD_LOGIC ) ; END COMPONENT ; END halfadd_package ;

22. ECE 331 - Digital System Design The Full Adder in VHDL (The Design File) LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE work.halfadd_package.all ; ENTITY fulladd IS PORT ( Cin, A, B : IN STD_LOGIC ; Sum, Cout : OUT STD_LOGIC ) ; END fulladd ; ARCHITECTURE Structure OF fulladd IS SIGNAL s1, c1, c2: STD_LOGIC ; BEGIN ha1 : halfadd PORT MAP ( A => A, B => B, Sum => s1, Cout => c1 ) ; ha2 : halfadd PORT MAP ( A, B, Sum, c2 ); Cout <= c1 OR c2 ; END Structure ;

23. ECE 331 - Digital System Design Multi-bit Adder Circuits

24. ECE 331 - Digital System Design Implementations of Multi-bit Adders: 1. Ripple Carry Adder 2. Carry Lookahead Adder

25. ECE 331 - Digital System Design Ripple Carry Adder

26. ECE 331 - Digital System Design Ripple Carry Adder Carry ripples from one column to the next 1 1 1 Carry-in 1 0 1 0 + 1 0 0 1 1 0 1 0 0 Carry-out

27. ECE 331 - Digital System Design Ripple Carry Adder x y x y x y 1 1 0 0 n – 1 n – 1 c 1 c c c c FA FA FA n ” 1 n 0 2 s s s n – 1 1 0 MSB position LSB position Carry-out Carry-in Carry ripples from one stage to the next

28. ECE 331 - Digital System Design Ripple Carry Adder n-bit Ripple Carry Adder Composed of n 1-bit Full Adders Carries ripple from LSB stage to MSB stage Delay ~ (n)*(delay of single FA stage) Area required is linear in n 4-bit Ripple Carry Adder Composed of 4 1-bit Full Adders

29. ECE 331 - Digital System Design The Ripple Carry Adder is slow! Why? How can the speed of the adder be increased?