1 / 55

ECE 551: Digital System Design & Synthesis

ECE 551: Digital System Design & Synthesis. Spring 2003 Lecture Materials Prepared by: Charles Kime, Kewal Saluja and Michael Schulte. ECE 551: Digital System Design & Synthesis. Lecture Set 1: Introduction Overview of Contemporary Digital Design Pragmatics 1.

soleil
Télécharger la présentation

ECE 551: Digital System Design & Synthesis

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. ECE 551: Digital System Design & Synthesis Spring 2003 Lecture Materials Prepared by: Charles Kime, Kewal Saluja and Michael Schulte

  2. ECE 551: Digital System Design & Synthesis • Lecture Set 1: • Introduction • Overview of Contemporary Digital Design • Pragmatics 1 ECE 551 Spring 2003

  3. ECE 551 - Digital System Design & SynthesisLecture 1.1 - Introduction • Overview • Course Purpose • Course Topics • Course Tools • Course Info ECE 551 Spring 2003

  4. Course Purpose • To provide knowledge and experience in performing contemporary logic design based on • Hardware description languages (HDLs) • HDL simulation • Automated logic synthesis • Timing analysis • With consideration for • Practical design and test issues • Chip layout issues • Design reuse for system-on-a-chip (SoC) ECE 551 Spring 2003

  5. Course Topics • Pragmatics of Digital Design • Hardware Modeling with the Verilog HDL • Event-Driven Simulation and Testbenches • Verilog Language Constructs and Delay • Behavioral Descriptions in Verilog • An Overview of VHDL • Logic Synthesis and Timing • Physical Design and Design Reuse ECE 551 Spring 2003

  6. Course Tools • Modelsim HDL Simulation Tools (Mentor) • Design Analyzer Synthesis Tools (Synopsys) • G11 Technology Library (LSI Logic) ECE 551 Spring 2003

  7. Course Information • Course Conduct • Standard Reference • The above plus all other course material can be found at http://courses.engr.wisc.edu/ecow/get/ece/551/kime/ • Be familiar with all! ECE 551 Spring 2003

  8. Lecture 1.2 – Contemporary Digital Design • Overview • Layout Lite • Application Specific Integrated Circuit (ASIC) Technologies • IC Costs • ASIC Design Flows • The Role of HDLs and Synthesis • The Role of IP Cores and Reuse • The Role of Physical Design • Summary ECE 551 Spring 2003

  9. Metal 3 Oxide Metal 2 Metal 1 Transistor Polysilicon Diffusion Substrate Channel Layout Lite - 1 • IC are produced from masks that correspond to geometric layouts produced by the designer or by EDA tools. • In CMOS, a typical IC cross-section: ECE 551 Spring 2003

  10. Transistor Channel Layout Lite - 2 • The layout corresponding to the cross-section: • The transistor is outlined in broad yellow lines. • Everything else is interconnect. ECE 551 Spring 2003

  11. STANDARD IC ASIC FULL CUSTOM STANDARD CELL GATE ARRAY, SEA OF GATES FPGA PLD IC Implementation Technologies SEMI- CUSTOM FIELD PROGRAMMABLE ECE 551 Spring 2003

  12. Distinguishing Features of IC Technologies - 1 • Implementation technologies are distinguished by: • The levels of the layout 1) transistors and 2) interconnect that are: • Common to distinct IC designs (L1) • Different for distinct IC designs (L2) • The use of predesigned layout cells • Predesigned cells are used (P1) • Predesigned cells are not used (P2) ECE 551 Spring 2003

  13. Distinguishing Features of IC Technologies - 2 • Implementation technologies are distinguished by: • Mechanism used for instantiating distinct IC designs: • Metallization (M) • Fuses or Antifuses (F) • Stored Charge (C) • Static Storage (R) ECE 551 Spring 2003

  14. Technologies in Terms of Distinguishing Features - 1 • Full Custom – P2, M • Transistors – L2, Interconnects – L2 • Standard Cell – P1, M • Transistors – L2, Interconnects – L2 • Gate Array, Sea of Gates – P1, M • Transistors – L1, Interconnects – L2 ECE 551 Spring 2003

  15. Technologies in Terms of Distinguishing Features - 2 • FPGA – P1, F or R • Transistors – L1, Interconnects – L1 • PLD – P1, F or C • Transistors – L1, Interconnects – L1 ECE 551 Spring 2003

  16. Technologies in Terms of Shared Fabrication Steps • Custom Fabricated Layers • Full Custom and Standard Cells – all layers are custom fabricated • Gate Arrays and Sea of Gates – only interconnect (metallization) layers custom fabricated • FPGAs and PLDs – nothing is custom fabricated • Consequences due to economy-of-scale: • Fab costs reduced for Gate Arrays and Sea of Gates • Fab costs further reduced for FPGAs and PLDs ECE 551 Spring 2003

  17. Layout Styles - 1 • Technologies in terms of layout styles: Standard Cell Adjustable Spacing … Megacells Gate Array - Channeled Fixed Spacing … Base Cell ECE 551 Spring 2003

  18. Layout Styles - 2 • Technologies in terms of layout styles: Gate Array - Channel-less (Sea of Gates) … Base Cell Gate Array - Structured … … Fixed Embedded Block ECE 551 Spring 2003

  19. IC Costs - 1 • An example: 10,000 gate circuit [1] • Fixed costs • Standard Cell - $146,000 • Gate Array - $86,000 • FPGA - $21,800 • Variable costs • Standard Cell - $8 per IC • Gate Array - $10 per IC • FPGA - $39 per IC ECE 551 Spring 2003

  20. IC Costs - 2 • An example: 10,000 gate circuit ECE 551 Spring 2003

  21. IC Costs – 3 • Why isn’t FPGA cheaper per unit due to economy-of-scale? • The chip area required by each of the successive technologies from Full Custom to FPGAs increases for a fixed-sized design. • The larger the chip area, the poorer the yield of working chips during fabrication • Also, due to increased sales, FPGA prices have declined since the mid-90’s much faster than the other technologies. ECE 551 Spring 2003

  22. Partition - Data- path &Control Draw Datapath Schematics * Define System Architecture Write Specifications Draw Control Schematics * Define State Diag/Tables Do Physical Design* Implement* Integrate Design* ASIC Design Flow - Traditional *Steps followed by validation and refinement ECE 551 Spring 2003

  23. Traditional Flow Problems • Schematic Diagrams • Limited descriptive power • Limited portability • Limited complexity • State Diagrams and Algorithmic State Machines • Limited complexity • Difficult to describe parallelism • Time-Intensive and Hard to Update ECE 551 Spring 2003

  24. How about HDLs Instead of Diagrams? - 1 • Hardware description languages (HDLs) • Computer-based programming languages • Model and simulate the functional behavior and timing of digital hardware • Synthesizable into a technology-specific netlist • Two main HDLs used by industry • Verilog HDL (C-based, industry-driven) • VHSIC HDL or VHDL (Ada-based, defense/industry/university-driven). ECE 551 Spring 2003

  25. How about HDLs Instead of Diagrams? - 2 • Advantages of HDLs • Highly portable (text) • Describes multiple levels of abstraction • Represents parallelism • Provides many descriptive styles • Structural • Register Transfer Level (RTL) • Behavioral • Serve as input for synthesis ECE 551 Spring 2003

  26. How about Synthesis instead of Manual Design? • Increased design efficiency • Potential for better optimization • Ability to explore more of overall design space • Reduces verification/validation problem • Are there disadvantages? ECE 551 Spring 2003

  27. HDL/Synthesis Design Flow - 1 Design Specification Verification: Functional Pre-Synthesis Sign-Off Design Partition Integration Synthesis and Technology Map Design Entry: HDL Behavioral Verification: Functional To next page ECE 551 Spring 2003

  28. HDL/Synthesis Design Flow - 2 Extract Parasitics Test Generation & Fault Simulation From prior page Verification: Post-Synthesis Physical Design Verification: Physical & Electrical Timing Verification: Post-Synthesis Design Sign-Off ECE 551 Spring 2003

  29. An Example from Industry • A G3 wireless processor was designed using the following methodology: • Entire processor modeled and tested using VHDL and C-based test programs • Processor functionality verified by synthesizing to an FPGA and running 3G wireless applications at 25 MHz • Processor timing and design feasibility verified by synthesizing to a standard cell library and running applications at 500 MHz. • Final version of processor implemented using a mix of standard cell and custom logic to achieve low-power and 800 MHz clock speed. ECE 551 Spring 2003

  30. Newer Technologies and Design Flows - SOC • System-on-a-Chip (SoC) • Designers use (Intellectual Property – IP) cores • RISC Core, DSP, Microcontroller, Memory • The main function is to glue many cores and generate/design only those components for which cores and designs may not be available • Used in ASIC as well as custom design environment • The issues relevant to this will be discussed near the end of the course ECE 551 Spring 2003

  31. Contemporary Design Flow - 1 Design Specification Preliminary Phys. Design Integration & Verification: Functional Design Partition Pre-Synthesis Sign-Off Design Entry: HDL Behavioral Select IP Cores Synthesis and Technology Map Verification: Functional To HDL/Synth Design Flow -2 ECE 551 Spring 2003

  32. Lecture 1.2 Summary • Application Specific Integrated Circuit (ASIC) Technologies • Provides a basis for what we will design • IC Costs • Gives a basis for technology selection • ASIC Design Flows • Shows the role of HDLs and synthesis • Provides a structure for • what we will learn • What we will do ECE 551 Spring 2003

  33. References • Smith, Michael J. S., Application-Specific Integrated Circuits, Addison-Wesley, 1997. ECE 551 Spring 2003

  34. Lecture 1.3 Pragmatics 1 • Pragmatics refers to practical design choices and techniques • Topics • Cell Libraries • Asynchronous Circuits • Three-State Logic and Hi-Z State ECE 551 Spring 2003

  35. Cells and Cell Libraries • What is a cell? • What is a cell library? • What appears in the cell library for each ASIC cell? ECE 551 Spring 2003

  36. What is a Cell? • Cells are the building blocks for digital designs • Come in different sizes, shapes and functions varying from transistors to large memory arrays or even a processor • Typically cells: • Small Scale: AND, OR, NAND, NOR, NOT, AOI, OAI, Flip-Flops, Latches • Medium Scale: Multiplexers, Decoders, Adders • Large Scale: Memories, Processors • Provided by ASIC vendors ECE 551 Spring 2003

  37. What is a Cell Library? • A database specifying and describing the target technology in the form of pre-designed objects called cells. Synthesis target technology. • In-Class Discussion: What are typical components in the database for each cell? ECE 551 Spring 2003

  38. Asynchronous Techniques • Delay-dependent design • Combinational hazards • Combinational hazard prevention • Asynchronous design ECE 551 Spring 2003

  39. A A Delay-Dependent Design 1 LA PA LA PA Example: Level-to-Pulse Converter(Delay-Based) ECE 551 Spring 2003

  40. Delay-Dependent Design 2 • Sometimes useful • But should be avoided • Time delays vary and so may: • Fail • Produce variable results, e. g. pulse length ECE 551 Spring 2003

  41. D C Q Delay-Dependent Design 3 • Level to Pulse Converter (Synchronous) LA PA Clock • Level on LA must be longer than a clock period and must not rise close to the positive clock edge. Ideally, synchronous with Clock. ECE 551 Spring 2003

  42. Combinational Hazards 1 • Example - Hazard in a Multiplexer A 1 B F C 1 B F ECE 551 Spring 2003

  43. Combinational Hazards - 2 • A circuit has a hazard if there exists an assignment of delays such that an unwanted signal transition (glitch), can occur. • Types of changes on combinational circuit inputs : • Single-input change (SIC) • Multiple-input change (MIC) • A SIC static hazard exists on a circuit output if in response to a SIC, the output momentarily changes to the opposite value. • Static 1-hazard – output value to remain at 1 • Static 0-hazard – output value to remain at 0 ECE 551 Spring 2003

  44. Combinational Hazards - 3 • Classification of Combinational Hazards • Static – SIC/MIC – output changes when it should remain fixed - output value within the “transition region of input changes is fixed. • Dynamic – SIC/MIC – output changes three or more times when it should change only once. • Essential – MIC – output changes when it should remain fixed – output value within the “transition region” of input changes not fixed. ECE 551 Spring 2003

  45. Combination Hazards - 4 • In-class Example: Illustration of static, dynamic and essential hazards ECE 551 Spring 2003

  46. Combinational Hazards - 5 • Consequences of Hazards • Signals with hazards within or entering asynchronous circuits (note that a flip-flop is an asynchronous circuit with respect to its clock signal!) • Cause incorrect state behavior • Extra state changes • Incorrect state changes • In-Class Example: Prevention of Hazards • Redundant Logic • Delay Dependence ECE 551 Spring 2003

  47. Asynchronous Design - 1 • Which of the following sequential circuits involve asynchronous design? • A circuit that has no global clock signal involved in its operation – state changes occur in response to input changes only. • A D flip-flop circuit • A circuit using clock gating on flip-flop clock inputs • A circuit with a clock which uses the clear and preset inputs on the flip-flops for other than initialization. ECE 551 Spring 2003

  48. Asynchronous Design - 2 • Because of the difficulty of eliminating hazards, it is very difficult to insure correct operation under all timing possibilities • Design must be done manually or by use of very specialized synthesis tools. • Therefore, avoid it if you can! • If you truly need it, investigate some of the more contemporary approaches[1] which avoid some of the many difficulties. ECE 551 Spring 2003

  49. Three-State and Other Hi-Z States • Three-state conflicts • Floating three-state nets and inputs • Pull-ups and Pull-downs • Bus keepers ECE 551 Spring 2003

  50. Three-State Conflicts - 1 • What are they and what are their effects? • Static – Chip damage or static power consumption • Dynamic – Dynamic or static power consumption 1 E0 1 E1 1 E0 0 1 E1 0 1 D0 E0 1 OUT D1 0 ECE 551 Spring 2003 1 E1

More Related