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Ge Semiconductor Devices for Cryogenic Power Electronics - V

Ge Semiconductor Devices for Cryogenic Power Electronics - V. WOLTE 6. ESA/ESTEC, Noordwijk, June 2004. R. R. Ward, W. J. Dawson, L. Zhu, R. K. Kirschman GPD Optoelectronics Corp., Salem, New Hampshire O. Mueller, M. J. Hennessy, E. K. Mueller MTECH Laboratories, Ballston Spa, New York

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Ge Semiconductor Devices for Cryogenic Power Electronics - V

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  1. Ge Semiconductor DevicesforCryogenic Power Electronics - V WOLTE 6 ESA/ESTEC, Noordwijk, June 2004

  2. R. R. Ward, W. J. Dawson, L. Zhu, R. K. KirschmanGPD Optoelectronics Corp., Salem, New Hampshire O. Mueller, M. J. Hennessy, E. K. Mueller MTECH Laboratories, Ballston Spa, New York R. L. Patterson, J. E. DickmanNASA Glenn Research Center, Cleveland, Ohio A. HammoudQSS Group Inc., Cleveland, Ohio Supported by NASA Glenn Research Center

  3. “Very Little of the Solar System (or the Universe) Is at Room Temperature.”

  4. Temperatures for Spacecraft

  5. TEMPERATURE CONTROL HEATING/COOLING SYSTEM CONVENTIONAL ELECTRONICS (HEAT STORAGE) THERMAL INSULATION COLD ENVIRONMENT “Traditional” Spacecraft

  6. CRYOGENIC ELECTRONICS COLD ENVIRONMENT “Cold” Spacecraft

  7. “Cold” Spacecraft Benefits • Eliminate heating, thermal control, isolation • Reduce power, weight, size, cost, complexity • Improve overall reliability • Reduce disruption of environment • Increase mission duration & capability

  8. Development Program

  9. Cryogenic Power Electronics • Active semiconductor devices for power circuits • For spacecraft power management & actuator control • Parameters • Power ~10 W • Temperature range 300 K to ~20 K • Device types • Diodes (P--N, 10 A, 300 V) • JFETs (lateral, vertical) • MISFETs (lateral, vertical) • BJTs (vertical implanted) • Based on Ge

  10. Why Use Ge?

  11. Why Ge Devices? • Applications require operation to 30 – 40 K range • Ge devices of all types can operate to low cryogenic temperatures (~20 K or lower) • Diodes • Field-effect transistors (JFETs, MISFETs) • Bipolar transistors • Performance advantages • P-N junction voltages are low • Mobility is high

  12. Ge Cryo Power Diodes

  13. Ge Cryo Power DiodesP--N Bulk Design Metal P+ implant Guard ring(s) N– ( ) Metal N+ implant

  14. Ge Diode - Forward I-V

  15. Ge Diode - Forward I-V

  16. Ge Diode - Forward I-V

  17. Ge Diodes - Forward Voltage

  18. Ge Diodes - Forward Voltage

  19. Ge Diodes - Reverse Breakdown

  20. Ge Diodes - Reverse Recovery

  21. Ge Diodes - Reverse Recovery

  22. Ge Diodes - Reverse Recovery

  23. Ge Cryo PowerField-Effect Transistors

  24. G D ~1.3 mm S S G Ge Cryo Power JFET or MISFET

  25. Ge Cryo Power JFETs(Junction Field-Effect Transistors)

  26. Source N epitaxial layer Drain Front gate P+ implant N+ implant P+ substrate Back gate contact P+ implant Ge JFET Cross-Section (n-channel)

  27. Ge JFET at 300 K (n-channel) 2 A ΔVGS = 1 V/step 10 V

  28. Ge JFET at 77 K (n-channel) 2 A ΔVGS = 1 V/step 10 V

  29. Ge JFET at 4 K (n-channel) 2 A ΔVGS = 1 V/step 10 V

  30. Ge JFET at 300 K (p-channel) 1 A ΔVGS = 1 V/step 50 V

  31. Ge JFET at 77 K (p-channel) 1 A ΔVGS = 1 V/step 50 V

  32. Ge JFET at 4 K (p-channel) 1 A ΔVGS = 1 V/step 50 V

  33. Trench Source P epitaxial layer Drain P+ implant N+ substrate Back gate contact (N+ implant) Ge JFET Cross-Section (p-channel)

  34. Ge JFET at 300 K (p-channel) 0.5 A ΔVGS = 2 V/step 20 V

  35. Ge JFET at 77 K (p-channel) 0.5 A ΔVGS = 2 V/step 20 V

  36. Ge JFET at 4 K (p-channel) 0.5 A ΔVGS = 2 V/step 20 V

  37. Ge Cryo Power MISFETs(Metal-Insulator-Semiconductor Field-Effect Transistors)

  38. Source Gate dielectric Drain Gate N+ implant P substrate Substrate contact (P+ implant) Lateral Ge MISFET Design (n-channel)

  39. Ge MISFET at 300 K (n-channel) 1 A ΔVGS = 1 V/step 20 V

  40. Ge MISFET at 77 K (n-channel) 1 A ΔVGS = 1 V/step 20 V

  41. Ge MISFET at 4 K (n-channel) 1 A ΔVGS = 1 V/step 20 V

  42. Ge MISFET Switching - 50 kHz ~30 W Load

  43. Ge MISFET Switching - 5 MHz ~30 W Load

  44. Ge MISFET at 300 K (p-channel) 1 A ΔVGS = 2 V/step 20 V

  45. Ge MISFET at 77 K (p-channel) 1 A ΔVGS = 2 V/step 20 V

  46. Ge MISFET at 4 K (p-channel) 1 A ΔVGS = 2 V/step 20 V

  47. Source Gate dielectric Gate P+ implant N epi P– substrate Drain P+ implant Vertical Ge MISFET Design(n-channel)

  48. Ge Vertical MISFET at 77 K (n-channel) 0.2 A ΔVGS = 2 V/step 10 V

  49. GeBipolar Junction Transistors

  50. Ge Bipolar – Double-Implant, Vertical Emitter N+ implant Base P implant N– substrate Collector N+ implant

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