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Zhangdong&Kangcai 2006.9 From China

Scicos-HDL is a toolbox which integrates the hardware circuit, algorithm and Scicos environment as a platform for digital circuit design, simulation and Hardware Description Language generation. Zhangdong&Kangcai 2006.9 From China. 01/13. 1 Characteristic.

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Zhangdong&Kangcai 2006.9 From China

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  1. Scicos-HDL is a toolbox which integrates the hardware circuit, algorithm and Scicos environment as a platform for digital circuit design, simulation and Hardware Description Language generation Zhangdong&Kangcai 2006.9 From China 01/13

  2. 1 Characteristic • Our project is based on Scilab/Scicos, Scilab4.0, for Windows & Linux； • It is a platform for digital circuit design, simulation and Hardware Description Language (VHDL and Verilog )generation ; • Inside libraries: Sequential logic library; Combinational logic library; Ipcore library; DSP blocks and simulation blocks, consisted of 50 blocks; • The original blocks of Scicos is allowed to be used in the circuit simulation ; • It can generate the documentations automatically including the description doc and the testbench for the circuit design (some); • Open interface for all the users by adding the truth table or IP core ,etc. 02/13

  3. 2 Install • First , you should install Scilab4.0 both in windows or Linux OS; • Download the newest release of Scicos- HDL from here: http://scicoshdl.sourceforge.net/ • The \install\install.txt will tell you how to install SCICOS-HDL. Digital system design basic library Combinational logic library Ipcore library Sequential logic library 03/13

  4. 3 How to use Scicos-HDL • All the using steps is as the same as that of Scicos, for modeling and simulation; • Just use the Verilog Compiler \VHDL Compiler to generate HDL code; • See file: \doc\scicosHdl-handbook.pdf of the package. 04/13

  5. 3 Examples Input signal Scicos Model Output signal 05/13

  6. HDL CODE generated by ScicosHDL 06/13

  7. The filter block synthesized in synplify pro 7.6 Gate net list RTL net list 07/13

  8. 3 use simulation with original Scicos blocks ADC group IN group Scicos-HDL OUT group DAC group Other Scicos blocks 08/13

  9. Other Example Scicos-HDL Model 09/13

  10. Other Example HDL Code 10/13

  11. Other Example HDL synthesized in other EDA tools 11/13

  12. 4 Hardware design flow of Scilab（Free or Open Source） ISE For Linux package … Scilab/Scicos FPGA/CPLD Compiler New Core ASIC 12/13

  13. Web Site: http://scicoshdl.sourceforge.net/ 5 Future Plan Project Email: scicoshdl@gmail.com Try out best to make Scicos-HDL as useful tool for the engineers; • Makes Scicos has hardware design and simulation function; • Optimize its compilers and support more Hardware Description Language ; • More blocks espacally for DSP; • Develop the automatic simulation blocks (virtual blocks); • Do the experiment about Scicos-HDL with a FPGA board; • Scicos-HDL has a unique meaning in the filed of open-resource EDA tools. 13/13

  14. Thank you http://scicoshdl.sourceforge.net Zhangdong&Kangcai 2006.9 From China END

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