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Advancements in IC Design and Radiation Hardness Evaluation at FNSPE-CTU

This document outlines the activities and developments from the newly formed hardware group at the Faculty of Nuclear Sciences and Physical Engineering of the Czech Technical University (FNSPE-CTU). It highlights the involvement of PhD students in critical projects such as radiation hardness evaluation, IC design, image processing, and chip testing. Additionally, the work being done includes sensor development and universal FPGA-based read-out systems, alongside collaborations in the ATLAS and AIDA initiatives. This collective effort is aimed at enhancing future detector technologies.

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Advancements in IC Design and Radiation Hardness Evaluation at FNSPE-CTU

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  1. Involvement in ATLAS upgrade M. Havránek on behalf of FNSPE-CTU Faculty of Nuclear Sciences and Physical Engineering of the Czech Technical University (FNSPE-CTU)

  2. Newly formed HW group at FNSPE • New laboratory at FNSPE • Part of the people came from Institute of Physics, ASCR • Involvement of PhD students: • M. Carna – evaluation radiation hardness • Z. Janoska – IC design • M. Hejtmanek – image processing (MediPix) • O. Korchak – TCAD simulations, chip testing • M. Marcisovsky – general advisor • Professionals: • V. Vrba – group leader • M. Havranek – IC design, institute representative • G. Neue – test system development • V. Kafka – IC design • L. Tomasek – sensor/chip testing, software development

  3. Experience obtained so far • Sensor development • - n on p sensor development • - TCAD simulations • Read-out system development • - universal FPGA based read-out system • IC design (150 nm technology) • - test structures (transistor arrays) • - charge sensitive amplifier • Evaluation of radiation hardness (150 nm CMOS technology) [1] 60Co Nucl. reactor [1] M. Carna et al: Radiation hardness evaluation of the commercial 150 nm CMOS process using 60Co source, IWORID2013 proceedings, accepted by JINST

  4. International collaboration • M. Havranek – 3 years stay at Bonn University* • Pixel capacitance measurement chip - PixCap • - IC design, development of measurement setup, capacitance measurements → publication [1] • Pixel FE development in 65 nm CMOS technology • - design of two 65 nm pixel FE prototypes (FE-T65-0, FE-T65-1) • - test system HW/SW development, chip characterization → publication [2] capacitance [fF] capacitance [fF] Diamond Si planar Diamond Si planar 25 µm 180 µm * Supervised by H. Krüger and T. Hemperek

  5. International collaboration • Depleted Monolithic Active pixel sensor • - design of DMAPS prototype chip EPCB01 • - sensor characterization, radiation test → publication [3] • Z. Janoska next month going to CPPM Marseille (HV MAPS testing) • References: • [1] M. Havranek et al:Measurement of pixel sensor capacitance with sub-femtofarad precision, • NIMA, vol. 714, 2013 • [2] M. Havranek et al: Pixel front-end development in 65 nm technology, JINST, vol 9, 2014 • [3] M. Havranek et al: DMAPS: a fully depleted monolithic active pixel sensor – analog performance • and characterization, submitted to JINST (05/2014)

  6. Role in the ATLAS Collaboration • Membership in RD53 Collaboration since April 2014 • RD53 Collaboration: • - design of the next generation of ATLAS/CMS Pixel chip • (phase 2 upgrade in ~2022) • Planned activities in RD53: • - studies of low power analog pixel front-end in 65 nm • - chip testing, small pixel sensor design • evaluation of radiation hardness with neutrons and gammas (60Co) • Participation in planned design of prototype pixel arrays prior to submission of large FE chip • Involvement in AIDA 2 Collaboration • - AIDA activities: sensor design on a p-substrate • - sensor testing, production, evaluation of radiation hardness • - supporting students working at projects for RD53

  7. Thank you for attention

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