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DSP Design Flows in FPGA. Objectives. Describe the advantages and disadvantages of three different design flows Use HDL, CORE Generator, or System Generator for DSP depending on design requirements and familiarity with the tools

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## DSP Design Flows in FPGA

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**DSP Design Flows in FPGA**This material exempt per Department of Commerce license exception TSU**Objectives**• Describe the advantages and disadvantages of three different design flows • Use HDL, CORE Generator, or System Generator for DSP depending on design requirements and familiarity with the tools • Explain why there is a need for an integrated flow from system design to implementation • Describe the System Generator and the tools it interfaces with • Build a model, simulate it, generate VHDL, and go through the design flow • Describe how Hardware in the Loop verification is beneficial in complex system design After completing this module, you will be able to:**Outline**• Using HDL • Using the Xilinx CORE Generator • Using the Xilinx System Generator for DSP • Lab 1: Creating a 12x8 MAC • HDL Co-Simulation • Hardware Verification • In System Debug • Resource Estimator • Upgrading to Sysgen 8.2 • Summary • Simulink Tips and Tricks**Implement your design using VHDL or Verilog**BehavioralSimulation HDL HDL Functional Simulation Synthesis TimingSimulation Implementation In-Circuit Verification Download HDL Design Verification**BehavioralSimulation**HDL HDL Synthesize the design to create an FPGA netlist Functional Simulation Synthesis TimingSimulation Implementation In-Circuit Verification Download Synthesis Design Verification**BehavioralSimulation**HDL HDL Functional Simulation Synthesis Translate, place and route, and generate a bitstream to download in the FPGA TimingSimulation Implementation In-Circuit Verification Download ImplementationDesign Verification**Outline**• Using HDL • Using the Xilinx CORE Generator • Using the Xilinx System Generator for DSP • Lab 1: Creating a 12x8 MAC • HDL Co-Simulation • Hardware Verification • Resource Estimator • Upgrading to Sysgen 8.2 • Summary • Simulink Tips and Tricks**CORE GeneratorDesign Verification**Instantiate optimized IP within the HDL code HDL BehavioralSimulation COREGen Functional Simulation Synthesis TimingSimulation Implementation In-Circuit Verification Download**HDL**BehavioralSimulation COREGen Functional Simulation Synthesis Synthesize, Implement, and Download the bitstream, similar to the original design flow TimingSimulation Implementation In-Circuit Verification Download Synthesize, Implement, DownloadDesign Verification**Xilinx IP Solutions**DSPFunctions MathFunctions MemoryFunctions P Multiplier Generator - Parallel Multiplier - Dyn Constant Coefficient Mult - Serial Sequential Multiplier - Multiplier Enhancements P Pipelined Divider P CORDIC P Asynchronous FIFO PBlock Memory modules P Distributed Memory P Distributed Mem Enhance P Sync FIFO (SRL16) P Sync FIFO (Block RAM) P CAM (SRL16) P CAM (Block RAM) $PAdditive White Gaussian Noise (AWGN) $PReed Solomon $ 3GPP Turbo Code $PViterbi Decoder PConvolution Encoder $P Interleaver/De-interleaver P LFSR P 1D DCT P 2D DCT P DA FIR P MAC P MAC-based FIR filter Fixed FFTs 16, 64, 256, 1024 points P FFT 16- to 16384- points PFFT - 32 Point P Sine Cosine Look-Up Tables $P Turbo Product Code (TPC) P Direct Digital Synthesizer P Cascaded Integrator Comb P Bit Correlator P Digital Down Converter BaseFunctions P Binary Decoder P Twos Complement P Shift Register RAM/FF P Gate modules P Multiplexer functions P Registers, FF & latch based P Adder/Subtractor P Accumulator P Comparator P Binary Counter IP CENTER http://www.xilinx.com/ipcenter Key:$ = License Fee,P = Parameterized,S = Project License Available,BOLD = Available in the Xilinx Blockset for the System Generator for DSP**Xilinx CORE Generator**List of available IP from or Fully Parameterizable**Fixed Placement &**Pre-defined Routing Fixed Placement Relative Placement I/Os Other logic has no effect on the core Guarantees I/O and Logic Predictability Guarantees Performance 200 MHz 200 MHz • Core Placement • Number of Cores • Device Size 200 MHz 200 MHz Xilinx Smart-IP Technology • Pre-defined placement and routing enhances performance and predictability • Performance is independent of:**Outputs**• .EDN (EDIF implementation netlist) • .XCO (core implementation data file / log file) • Optional: • .ASY Foundation or Innoveda symbols • .VEO Verilog instantiation template • .V Verilog behavioral simulation model • .VHO VHDL instantiation template • .VHD VHDL behavioral simulation model**Outline**• Using HDL • Using the Xilinx CORE Generator • Using the Xilinx System Generator for DSP • Lab 1: Creating a 12x8 MAC • HDL Co-Simulation • Hardware Verification • In System Debug • Resource Estimator • Upgrading to Sysgen 8.2 • Summary • Simulink Tips and Tricks**The Challenges for a DSP Software Platform**• Industry Trends • Trend towards platform chips (FPGAs, DSP) resulting in greater complexity • Highly flexible systems required to meet changing standards • Multiple design methodologies - control plane/datapath • Challenges in modeling and implementing an entire platform • Hardware in the loop verification is useful in complex system design and System Generator supports it • System Design Challenges • Leveraging legacy HDL code • Modeling & implementing control logic and datapath • No expert exists for all facets of system design**MATLAB**• MATLAB™, the most popular system design tool, is a programming language, interpreter, and modeling environment • Extensive libraries for math functions, signal processing, DSP, communications, and much more • Visualization: large array of functions to plot and visualize your data and system/design • Open architecture: software model based on base system and domain-specific plug-ins**MATLAB**• Frequency response of input sound file**Simulink**• Simulink™ - Visual data flow environment for modeling and simulation of dynamical systems • Fully integrated with the MATLAB engine • Graphical block editor • Event-driven simulator • Models parallelism • Extensive library of parameterizable functions • Simulink Blockset - math, sinks, sources • DSP Blockset - filters, transforms, etc. • Communications Blockset - modulation, DPCM, etc.**MATLAB/Simulink**Real time frequency response from a microphone: emphasizes the dynamic nature of Simulink**Traditional Simulink FPGA Flow**System Verification System Architect GAP Simulink FPGA Designer HDL Synthesis Verify Equivalence Functional Simulation Timing Simulation Implementation In-Circuit Verification Download**System Generator for DSPOverview**• Industry’s system-level design environment (IDE) for FPGAs • Integrated design flow from Simulink to bit file • Leverages existing technologies • Matlab/Simulink from The MathWorks • HDL synthesis • IP Core libraries • FPGA implementation tools • Simulink library of arithmetic, logic operators and DSP functions (Xilinx Blockset) • Bit and cycle true to FPGA implementation • Arithmetic abstraction • Arbitrary precision fixed-point, including quantization and overflow • Simulation of double precision as well as fixed point**System Generator for DSP Overview**VHDL code generation for Virtex-4™, Virtex-II Pro™, Virtex™-II, Virtex™-E, Virtex™, Spartan™-3E, Spartan™-3, Spartan™-IIE and Spartan™-II devices • Hardware expansion and mapping • Synthesizable VHDL with model hierarchy preserved • Mixed language support for Verilog • Automatic invocation of CORE Generator to utilize IP cores • ISE project generation to simplify the design flow • HDL testbench and test vector generation • Constraint file (.xcf), simulation ‘.do’ files generation • HDL Co-Simulation • Verification acceleration using Hardware in the Loop**ISIM**System Generator for DSP Platform Designs**Simulation**ISIM RTL VHDL & Cores The SysGen Design Flow DSP Development Flow 1. Develop Algorithm & System Model Simulink MDL 2. Automatic Code Generation HDL Test Bench 3. Xilinx Implementation Flow Bitstream Download to FPGA**HDL**System Generator Implementation Download System Generator Based Design Flow MATLAB/Simulink System Verification Synthesis Functional Simulation TimingSimulation In-Circuit Verification**HDL**System Generator HDL-CoSimulation Implementation Download System Generator Based Design Flow MATLAB/Simulink • Files Used • Configuration file • VHDL • IP • Constraints File System Verification Synthesis Functional Simulation TimingSimulation In-Circuit Verification * ModelSim helper block not needed when ISIM simulator is used**HDL**System Generator Implementation Download System Generator Based Design Flow MATLAB/Simulink • Files Used • Configuration file • VHDL • IP • Constraints File System Verification Synthesis Functional Simulation TimingSimulation In-Circuit Verification**Creating a SystemGenerator Design**• Invoke Simulink library browser • To open the Simulink library browser, click the Simulink library browser button or type “Simulink” in MATLAB console • The library browser contains all the blocks available to designers • Start a new design by clicking the new sheet button**Creating a SystemGenerator Design**• Build the design by dragging and dropping blocks from the Xilinx blockset onto your new sheet. • Design Entry is similar to a schematic editor Connect up blocks by pulling the arrows on the sides of each block**Finding Blocks**• Use the Find feature to search ALL Simulink libraries • Xilinx blockset has nine major sections • Basic elements • Counters, delays • Communication • Error correction blocks • Control Logic • MCode, Black Box • Data Types • Convert, Slice • DSP • FDATool, FFT, FIR • Index • All Xilinx blocks – quick way to view all blocks • Math • Multiply, accumulate, inverter • Memory • Dual Port RAM, Single Port RAM • Tools • ModelSim, Resource Estimator**Configure Your Blocks**• Double-click or go to Block Parametersto view a block’s configurable parameters • Arithmetic Type: Unsigned or twos complement • Implement with Xilinx Smart-IP Core (if possible)/Generate Core • Latency: Specify the delay through the block • Overflow and Quantization: Users can saturate orwrap overflow. Truncate or Round Quantization • Override with Doubles: Simulation only • Precision: Full or the user can define the number of bits and where the decimal point is for the block • Sample Period: Can be inherent with a “-1” or must be an integer value • Note: While all parameters can be simulated,not all are realizable**Values Can Be Equations**• You can also enter equations in the block parameters, which can aid calculation and your own understanding of the model parameters • The equations are calculated at the beginning of a simulation • Useful MATLAB operators • + add • - subtract • * multiply • / divide • ^ power • pi (3.1415926535897.…) • exp(x) exponential (ex)**Value = -2.261108…**Format = Fix_16_13 -22 21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 1 0 1 1 0 1 1 1 1 0 1 0 0 1 0 1 (Sign: Fix = Signed Value UFix = Unsigned value) Integer Fraction Format = Sign_Width_Decimal point from the LSB Important Concept 1:The Numbers Game • Simulink uses a “double” to represent numbers in a simulation. A double is a “64-bit twos complement floating point number” • Because the binary point can move, a double can represent any number between +/- 9.223 x 1018 with a resolution of 1.08 x 10-19 …a wide desirable range, but not efficient or realistic for FPGAs • Xilinx Blockset uses n-bit fixed point number (twos complement optional) • Design Hint:Always try to maximize the dynamic range of design by using only the required number of bits Thus, a conversion is required when communicating with Xilinx blocks with Simulink blocks (Xilinx blockset MATLAB I/O Gateway In/Out)**What About All ThoseOther Bits?**• The Gateway In and Out blocks support parameters to control the conversion from double precision to N - bit fixed point precision DOUBLE 24 23 22 21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 -26 25 . . . . . . . . 1 1 1 1 1 0 1 1 0 1 1 1 1 0 1 0 0 1 0 1 OVERFLOW QUANTIZATION • Saturate • Wrap • Flag for Error • Truncate • Round -22 21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 1 0 1 1 0 1 1 1 1 0 1 0 FIX_12_9**Other Type: Boolean**• The Xilinx Blockset also uses the type Boolean for control ports like CE and RESET • The Boolean type is a variant on the 1-bit unsigned number in that it will always be defined (High or Low). A 1-bit unsigned number can become invalid; a Boolean type cannot**Knowledge Check**Using the technique shown, convert the following fractional values… • Define the format of the following twos complement binary fraction and calculate the value it represents • What format should be used to represent a signal that has: • Fill in the table: Format = < _ _ > 1 1 0 0 0 1 1 0 1 0 1 1 Value = a) Max value: +0.999… Min value: -0.999… Quantized to 12 bit data b) Max value: 0.8 Min value: 0.2 Quantized to 10 bit data c) Max value: 278 Min value: -138 Quantized to 11 bit data Format = < _ _ > Format = < _ _ > Format = < _ _ >**Answers**• Define the format of the following twos complement binary fraction and calculate the value it represents • What format should be used to represent a signal that has: • Fill in the table: Using the technique below, convert the following fractional values Format = < Fix_12_5 > 1 1 0 0 0 1 1 0 1 0 1 1 Value = -917 = -28.65625 32 c) Max value: 278 Min value: -138 Quantized to 11-bit data a) Max value: +1 Min value: -1 Quantized to 12-bit data b) Max value: 0.8 Min value: 0.2 Quantized to 10-bit data Format = < FIX _12_10 > Format = <UFIX_10_10> Format = < FIX _11_1>**Creating a SystemGenerator Design**SysGen Data Path andhelper blocks Simulink Sinks Simulink Sources Gateway blocks used to interface between Simulink and SysGen blocks**System Generator Design**Start simulation by pressing the play button • Designs may have levels of hierarchy • Double click to “push” into a subsystem • All SysGen design must contain a System Generator block • Used to set global netlisting attributes**Important Concept 2:Sample Period**• Every SysGen signal must be “sampled”; transitions occur at equidistant discrete points in time called sample times • Each block in a Simulink design has a “Sample Period” and it corresponds to how often that block’s function is calculated and the results outputted • This sample period must be set explicitly for: • Gateway in • Blocks w/o inputs (note: constants are idiosyncratic) • Sample period can be “derived” from input sample times for other blocks**Important Concept 2:Sample Period**• The units of the sample period can be thought of as arbitrary, BUT a lot of Simulink source blocks do have an essence of time • For example, a sample period of 1/44100 means the block’s function will be executed every 1/44100 of a sec • Remember Nyquist Theorem (Fs 2fmax) when setting sample periods • The sample period of a block DIRECTLY relates to how that block will be clocked in the actual hardware. More on this later**Setting the Global Sample Period**• The Simulink System Period MUST be set in the System Generator token. For single rate systems it will be the same as the Sample Periods set in the design. More on Multi Rate designs later Sample Period = 1**SysGen Token**Slave Controls Master Controls “Simulink System Period” MUST be set correctly for simulation to work**Using the Scope**• Click Properties to change the number ofaxes displayed and the time range value(X-axis) • Use the Data History tab to control how many values are stored and displayed on the scope • Also can direct output to workspace • Click Autoscale to quickly let the toolsconfigure the display to the correct axisvalues • Right-click on the Y-axis to set its value**Design and Simulatein Simulink**Push “play” to simulate the design. Go to “Simulation Parameters” under the “Simulation” menu to control the length of simulations**Generate the HDL Code**Once complete, double-click the System Generator token • Select the target device • Select Synthesis Tool • Set the FPGA clock period desired • Select to generate the testbench • Generate the VHDL**System Generator Output Files**• Design files • <design>.VHD/ .V : HDL design files • <design>_cw.VHD/.V: Top-level HDL wrapper that contains clock circuit and SysGen Design • .EDN and .NGC: Core implementation file • <design>_cw.XCF : Xilinx constraints file for timing and location constraints • Project files • <design>_cw.ISE : Project Navigator project file • .PRJ: Synthesis project files for XST and Synplify • .TCL : Scripts for Synplify and Leonardo project creation • Simulation files • .DO : Simulation scripts for MTI • .DAT : Data files containing the test vectors from System Generator • <design>_tb.VHD/.V : Simulation testbench**Outline**• Using HDL • Using the Xilinx CORE Generator • Using the Xilinx System Generator for DSP • Lab 1: Creating a 12x8 MAC • HDL Co-Simulation • Hardware Verification • In System Debug • Resource Estimator • Upgrading to Sysgen 8.2 • Summary • Simulink Tips and Tricks**Labs 1: Generating a MAC**• You will generate the MAC using the Xilinx System Generator for DSP • Compare the implementation results • Contrast the design methodologies**Lab 1**• Goals: Gain familiarity with the SysGen v8.1 and its design flow, including ProjNav, synthesis tools (XST), ModelSim simulators, and the ISE implementation tools. Use Resource Estimator to estimate resources used by the design. Familiarize with hardware in the Loop flow • Background: The multiply-accumulate (MAC) operation is fundamental in digital signal processing and numerous other applications a c = S aibi c + b N-1 i yn = S xn-i hi For example, the output of a digital filter with impulse response hi and input sequence xi, is given by: i=0

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