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DSP Design Flow System Generator for DSP

DSP Design Flow System Generator for DSP. Course Agenda. Objectives. Identify Xilinx FPGA features that lend to high-performance DSP design Describe the System Generator design flow Understand the basics of Simulink List various Xilinx blocks available for basic design capture

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DSP Design Flow System Generator for DSP

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  1. DSP Design FlowSystem Generator for DSP Course Agenda This material exempt per Department of Commerce license exception TSU

  2. Objectives • Identify Xilinx FPGA features that lend to high-performance DSP design • Describe the System Generator design flow • Understand the basics of Simulink • List various Xilinx blocks available for basic design capture • Interface System generator designs with Simulink sources and sinks • Identify the high-level blocks available for FIR designs • Add control logic to a System Generator Design • Design a multiple-clock-based System Generator system • Perform hardware-in-the-loop and improve productivity After completing this course, you will be able to: Course Introduction 2

  3. Day one Agenda • FPGAs for DSP • Introduction to System Generator • Simulink Basics • Lab 1: Using Simulink • Basic Xilinx Design Capture • Lab 2: Getting Started with Xilinx System Generator • Signal Routing • Lab 3: Signal Routing Course Introduction 3

  4. Day Two Agenda • Implementing System Control • Lab 4: Implementing System Control • Multi-Rate Systems • Lab 5: Designing a MAC-Based FIR • Filter Design • Lab 6: Designing a FIR Filter Using the DA FIR Block Course Introduction 4

  5. Prerequisites • Fundamental DSP knowledge (ie. FIR filters) • Digital design and FPGA knowledge • Basic understanding of the Matlab tools Course Introduction 5

  6. Platform Support • ISE 13.2 • System Generator 13.2 • Matlab R2010a or later • Xilinx University board* • Spartan-3E Starter Kit Board • Supported Operating Systems • Windows XP (SP2) (32/64 Bit) • Windows Vista Business (32/64 Bit) • Red Hat Enterprise Linux 4 (32/64 Bit) • SUSE Linux Enterprise (32/64 Bit) *Requires plugin to perform hardware in the loop verification

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