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CRKit R4 Architecture Review for Packet Processing Efficiency

This document, created by WINLAB at Rutgers University, provides an in-depth review of the CRKit R4 architecture, focusing on packet processing efficiency. It covers specifications such as the top level design, memory allocation per application, packet processor details, IP/SID/Port ID tables, and more. This review aims to enhance understanding and optimization of the CRKit R4 system for improved performance.

arabella-elvery
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CRKit R4 Architecture Review for Packet Processing Efficiency

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  1. CRKit R4 Architecturerev 0.23 WINLAB – Rutgers University Date : August 25, 2011

  2. R4 - top level

  3. R4 - top level 64x32 – .25KB per app 512x32 – 2KB 128x34 – .5KB 1Kx34 – 4KB 64x32 – .25KB per app 2Kx34 – 8KB

  4. R4 – Packet Processor 128x32 – .5KB per app 4Kx32 – 16KB per app 128x32 – .5KB 4Kx32 – 16KB 128x32 – .5KB 4Kx32 – 16KB IP table 128x32 –.5KB SID table 128x32 –.5KB Port ID table 128x32 –.5KB 128x32 – .5KB per app 4Kx32 – 16KB per app

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