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CRKit R4 Architecture rev 0.2

CRKit R4 Architecture rev 0.2. WINLAB – Rutgers University Date : May 7, 2011. R4 - top level. R4 - app2host. if (IP == 1) then Enable IP processing (append dIP, sIP & UDP) Forward dMAC/sMAC else Disable IP Processing Forward dMAC/sMAC endif. Lookup using PortID.

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CRKit R4 Architecture rev 0.2

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  1. CRKit R4 Architecturerev 0.2 WINLAB – Rutgers University Date : May 7, 2011

  2. R4 - top level

  3. R4 - app2host if (IP == 1) then Enable IP processing (append dIP, sIP & UDP) Forward dMAC/sMAC else Disable IP Processing Forward dMAC/sMAC endif Lookup using PortID dMAC/sMAC from IP Processor VRT Receiver Lookup using PortID if (V == 1) then Enable VITA formatting else Disable VITA formatting endif

  4. R4 - app2host MMU drdy - data ready dreq - data request CMD FORMAT PortID: 0-3 - APP0-3 ports 4-15 – PCORE ports size : data size in bytes ptr : pointer to data in memory To prefetch configuration settings at VITA emitter and IP Processor. Next prefetch can commence during current payload transfer

  5. R4 - host2app CMD FORMAT Ethertype = 0x0800 - IPv4 0x0806 - ARP If (V==1) then VITA context packet Else non-VITA packet use ethertype field for further parsing Endif; • Forward ethernet payload if : • incoming MAC = dMAC • incoming MAC = Broadcast • Append Ethertype field (16-bit) to ethernet payload if (ethertype == IPv4 & Incoming IP == dIP & UDP = 1000) then forward UDP payload to VITA Receiver else forward packet to PCORE

  6. R4 - PCORE PCORE – RMAP RD/WR IP Host -> PCORE (UDP-1001) RTYPE: 0x2000 – RMAP READ 0x2001 – RMAP WRITE RADDR: Register address RDATA: Register data Address Decoding IP PCORE -> Host (UDP-1000)

  7. R4 - APP

  8. R4 – Memory Map Upper 4 MSBs : 0x0-0x1 : PCORE 0x2 : CRKIT Others : Unused 0x0 : CMN 0x1 : ETH 0x2 : PKT 0x3-0xA : APP 0xB : DAC IF 0xC : ADC IF INT SPI, LED DCM/CLOCK CE

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