System-On-a-Programmable-Chip (SOPC) Implementation of the Silicon Track Card (STC)

1. System-On-a-Programmable-Chip (SOPC)Implementation of the Silicon Track Card (STC) Thesis Defense ByArvindh-kumar Lalam Department of Electrical and Computer Engineering Florida A&M University – Florida State University College of Engineering

2. Outline • DZERO Experiment • Silicon Track Card (STC) • SOPC Implementation and Validation • Content Addressable Memory (CAM) • Hit-Filter Implementation using a CAM • Results and Conclusions

3. Proton Anti-proton Collision • Study the properties of known particles Eg. ‘top’ quark • Look for the unknown

4. DZERO (D0) Experiment • The DZERO Experiment is conducted in Tevatron Collider, at Fermi National Acceleration Laboratory • proton& anti-protonare made to collide at high velocities in the TeVatron collider • The beams cross every 132 ns The TeVatron Collider

5. Silicon Tracker Fiber Tracker • Silicon Tracker (SMT) • Contains Silicon charge collectors - “strips” • Fiber Tracker (CFT) • Identifies trajectory information - “tracks” D0 Detector

6. Particle tracks • Cross-section of Fiber Tracker (CFT)

7. Trigger Detector Level 1 Level2 SMT L2 Cal L1 CAL L2 Ps preprocess SMT data L1 CFT find clusters CAL L2 Global Level 3 L2 CFT associate clusters with L1CTT tracks L1CFT L2 STT FPS/ CPS fit trajectories L1 Muon L2 Muon L3 L1 FPD L2CFT CFT L1 Framework SMT Muon FPD D0 Trigger

8. STC L1CFT SMT FRC (roads) preprocess SMT data find clusters centroids associate clusters with L1CTT tracks (finds hits) fit trajectories TFC L2CFT The Level_2 STT L3

9. CFT H Layer 2 mm road hits CFT A Layer centroids SMT Layers “Si” strips D0 Trigger - STC • “road” : Track information translated for the STC • “clusters” : Groups of strips • “centroid”: Centroid of a cluster • “hit” : A centroid that falls in a road

10. STC - Functionality • Reformats received “strip” data • Finds “Clusters” and their “centroids” • Identifies “hits” • Stores intermediate data for debugging • Implements a contention scheme • Several STCs function simultaneously • Operates at PCI 33 MHz

11. Control Lines Main Control Data Lines Control Lines Control Logic Handshake Signals Roads from FRC SMT Data Downloaded Parameters Centroid Finder Hit Filter Strip Reader Hits L3 Buffers To L3 STC - Main Data Path

12. Control and Feedback Signals . . . . Control Logic 7 . . . 1 0 Channel 0 (STC0) Channel 1 (STC1) Channel 7 (STC7) . . . . . . To rest of L2STT SMT Data (strip information) Control Logic and Channels • Control Logic designed at BU acts as an interface • Each Control Logic controls 8 Channels (STCs) • STC receives SMT data directly from SMT • “commom data bus” is used to download hits

13. System-On-a-Programmable-Chip (SOPC) • Discrete PCB components? • SOPC • Altera APEX II EP2A90 7M gates: 1.5Mbits SRAM • Xylinx Virtex E XC2V10000 10M gates: 3.4 Mbits SRAM • Altera APEX 20KE • EP20K600EBC652-1X • Accommodates 1 STC

14. SOPC - Advantages • The circuit can be fit into a single device • Occupies smaller area on the board • Board-design interconnects are less complex • Internal propagation delays are predictable

15. Computer Aided Design Tools • Entry and Functional Simulations: Quartus II, Active HDL 4.2 • Entry in VHDL/Schematics • Synthesis: Quartus II, Synopsys FPGA Express • Simulation and Configuration: Quartus II

16. Prototype Testing Board SOPC Implementation of STC • Control Logic • BU • Silicon Track Card • FAMU-FSU COE • Used Test memory space to store test vectors of SMT data

17. SOPC Implementation - Hit download

18. SOPC Implementation - Result Contention is successfully resolved

19. STC - Resources

20. Address Data Found 00 01 10 11 100 111 001 000 1 Data 3 Encoded Address 2 1 - 0 - 0 - 1 001 - 010 - 011 - 100 100 111 001 000 100 111 001 000 100 111 001 000 10 - X- X - 00 4 x 3 CAM with Encoded Output Content Addressable Memory(CAM) • A memory like RAM and FIFO • Takes data as input and provides the location • Output can be “encoded” or “unencoded” • A “found” signal is used to signal presence of data

21. Address (binary) Data represented in the CAM Equivalent Word decimal binary 00 1 0 0 0 1 0 0 0 1 01 2, 3 0 0 1 0 0 0 1 1 0 0 1d 10 4, 5, 6, 7 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0 1d d 11 0, 4, 8, 12 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 d d 0 0 Don’t cares • Don’t-cares can be used to represent multiple digital words • A don’t-care(d)represents both ‘1’ and ‘0’ • CAMs that accommodate don’t-cares are called Ternary CAMs • Eg: APEX CAM

22. Address Data Found 0 - 00 01 10 11 0001 001d 01dd dd00 - 1001 1 0001 001d 01dd dd00 Data 4 Encoded Address X- 2 1 - 1 1100 - 0100 0001 001d 01dd dd00 0001 001d 01dd dd00 11 - 10, 11 APEX CAM • Memory blocks of Altera’s APEX chip can be used as a Ternary CAM • The data can be stored in two ways • During power-up (using an .mif file) • During run-time

23. 21…11 10 ... 0 Upper Address Lower Address Road Word Previous Hit Filter • Receives roads and centroids • Internally stores roads • Uses ‘hit-match’ modules to find if a centroid falls in the roads • When a centroid falls in a road, it is a hit • Each ‘hit-match’ generates a bit ‘1’ for hit

24. road word 22 road select 6 Hit-Format (Encoder) centroid 11 comparator word hit 46 32 Comparator Module 46 “hit-match” modules in parallel Previous Hit Filter – Block Diagram • Contains 46 ‘hit-match’ modules • Each of the centroids is checked in all roads • The locations of ‘1’s are encoded to generate a hit-word • Hit-format, designed in VHDL, uses Finite State Machine • Hit-format module sequentially searches for hits.

25. Hit Filter – CAM-only model • Uses memory blocks instead of a combinational circuit (comparator) • Set of all the words existing between the road boundaries is called a “road-set” • Each road-set can be minimized to 12 words by using don’t cares • “road-sets” of each road are stored in the memory

26. Actual road-set Minimized road-set 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 2 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 d 3 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 d d 4 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 1 d d d 5 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 d d d d 6 0 1 0 0 0 0 0 0 1 1 1 1 1 1 0 1 d d d d d 7 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 0 d d d d d 8 1 1 0 0 0 0 0 1 1 0 1 1 1 1 1 1 0 d d d d 9 1 1 1 0 0 0 0 1 1 1 0 1 1 1 1 1 1 0 d d d 10 1 1 1 1 0 0 0 1 1 1 1 0 1 1 1 1 1 1 0 d d 11 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 0 d 12 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Minimized Road-Set 1000 0000001 . . 1000 1111110

27. Road-set word found Road-set Generator Hit create 11 CAM road Control signals location 22 10 centroid 11 hit 32 CAM-only model – Implementation

28. CAM-only Model - Functionality • Storing roads • The road-set is minimized by using the “don’t cares” • The minimized road-set is stored in an APEX CAM • The CAM needs 50 clock cycles to store each road-set • Checking for hits • Each of the centroids is given as input to the CAM • If the centroid is found in the road-set, CAM returns all the encoded locations. • CAM takes only two clock cycles to find the location of first hit

29. Hit Filter – With New Encoder • Uses previous comparator block and a new “hit-word generator” block • The locations of ‘1’s in the comparator word are encoded using a CAM

30. road word 22 road select 6 Hit-Word Generator (Encoder) centroid 11 comparator word hit 46 32 Comparator Module 46 “hit-match” modules in parallel Hit Filter – Implementation

31. Address Data Found 00 01 10 11 d d d 1 d d 1 d d 1 d d 1 d d d 1 Data 4 Encoded Address 2 1 - 0 - 0001 - 0000 d d d 1 d d 1 d d 1 d d 1 d d d d d d 1 d d 1 d d 1 d d 1 d d d 3 2 1 0 00 - X- 0 d d d 1 4 x 4 Encoder Map 1 1 d d 1 d - 1001 2 d d d d 1 d d 1 d d 1 d d 1 d d d 1 d d 3 1 d d d 00, 11 CAM as Encoder

32. 31 x 31 Encoder Map 15 x 15 Encoder Map Hit Filter Encoder Map 46 x 46 Encoder Map

33. HIT Control Signals HIT GENERATOR 32 31 CAM 31x31 6 15 CAM 15x15 5 Comparator Word 46 Hit-Word Generator

34. Hit Filter Results Number of clock cycles required for storing road information * This depends on the upper and lower words of the road. The quoted figures correspond to the worst possible case.

35. Hit Filter Results Number of clock cycles required for finding hits

36. STC 6 consecutive roads 46 roads 6 distributed roads Event1 Event2 Event1 Event2 Event1 Event2 Previous 4.878s 15.0s 16.48s 76.03s 11.636s 51.78s Upgraded 4.03s 6.909s 5.242s 19.06s 4.03s 6.909s % decrease in time taken 17% 54% 68% 75% 65% 87% STC Results • Event 1 : SMT data for a simple event • Event 2 : SMT data for a complex event

37. Conclusions • SOPC implementation was successfully verified • The upgraded STC shows an improvement of upto 87%

38. Future Work • The number of roads Hit-Filter can accommodate can be increased

39. Acknowledgements • National Science Foundation and the US Department of Energy. • Boston University • Faculty: Heintz, Narain, Popkov • Engineers: Earle, Hazen • Students: Kevin, Zabi • Florida State University – Physics • Faculty: Adams, Prosper, Wahl • Postdocs: Tentindo-Repond • Florida A&M University – Florida State University COE • Faculty: Perry • Students: Lolage, Meyers, Roper, Saunders • Altera, Aldec, Synopsys