1 / 18

Parallel Satellite Image Compression System on Programmable Chip

Develops a parallel processing system on a chip for compressing satellite images to meet the high input data rate and image size requirements. The system architecture involves dividing the image into strips and employing multiple compression units for efficient processing. Implementation includes modularity and scalability for future systems.

kemp
Télécharger la présentation

Parallel Satellite Image Compression System on Programmable Chip

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Parallel compressing system for satellite on programmable chip Part A Yifat Manzor & Reshef Dahan Supervisor: Eran Segev

  2. Satelliteimage Input Data ratefrom one sensor line • B/W Picture • Range – 2.5 km width • Velocity - 8 km/sec • 4 Pixels per 1m² 5,000 pix 80 Mpixel image 16,000 lines/sec Rate = 80 Mpix/sec Streaming Data 12-bit per pixel

  3. System demands:»80Mpix/sec input data rate.» Image width – 5000 pixelADV202, compressing device inreversible mode, capabilities:»27 Mpix/sec maximum input data rate» 25 MByte/sec maximum output rate » Maximum image width – 4096 pixel » Maximum image length – infinity

  4. Solution MAIN IDEA 1667pix 1667pix 1666pix To generate parallel processing by separating the picture to 3 compressors Tile 16,000 lines/sec 3

  5. System Description Xilinx’s development board – Virtex2Pro camera ADV202 Rocket I\O FPGA ADV202 ADV202 Memory

  6. FPGA block diagram Compression Unit Compresseddata Rocket I/O Compression Unit MERGER DIVIDER Compression Unit

  7. Implementation Modularity • Strip size and rate compatible with the compressor’s abilities. • Function block in design scalability • Merge and Divide protocol • Infrastructure for future systems requiring working in higher rates and/or handling larger image size.

  8. ImplementationCont. Power saving in space • Compressing units – minimum as possible. • Buffer in/out - minimum storing space.

  9. Divider Compression Unit Compression Unit MERGER DIVIDER Compression Unit • Separates the streamed data to 3 infinite, equal • width strips. • Separation technique - cyclic, streams 1/3 of • every line to a different compression unit.

  10. Divider - Architecture compression unit 1 Rocket IO Divider_unit compression unit 2 compression unit 3 80MHz

  11. compression unit Compression Unit • rate coordinator between the • divider and the • ADV202 input rate. • ADV202 model – imitates the • real ADV202 interface. • rate coordinator between the ADV202 output rate • and the merger. • communicates with the merger for sending • compressed data packages. Compression Unit MERGER DIVIDER Compression Unit

  12. Compression unit - Architecture From divider 12 bits 8 bits To/frommerger adv_202 model comp_data buff funnel 27MHz 25MHz 80MHz 80MHz Tomerger Interrupt_generator

  13. merger Compression Unit • Merges 3 streaming data • channels to a single • streaming data. • Manages an interrupt queue. • Draws fixed size, compressed packages from the • compression units. • Generates a header to every drawn package. MERGER Compression Unit DIVIDER Compression Unit Output: package compressed data header

  14. Merger - Architecture header generator 80MHz To/fromunit0 Compressedoutput To/fromunit1 calculator To/fromunit2 25MHz

  15. Merger – Architecture cont. To\from header generator calculator Data to/fromunit0 output generator Compressedoutput Data to/fromunit1 Data to/fromunit2 80MHz Interrupt from unit 0 Interrupt from unit 1 queue generator queue Interrupt from unit 2 25MHz

  16. Scalabilityaspect - 8 sensors lines Comp. Unit Comp. Unit DIVIDER MERGER Comp. Unit ON BOARD POWER PC 1-2 / GLOBAL MERGER

  17. Testing Environment Check Results Virtex2Pro Comp. Unit Rocket I/O Comp. Unit memory Generator DIVIDER MERGER Comp. Unit

  18. Status

More Related