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Implementation of DSP Systems Course Seminar

Implementation of DSP Systems Course Seminar. ECE Department Tehran University Spring 2005. A Practical Example Of DSP System Design, ADSL Modem DMT Engine. Outline. A glance at ADSL modems structure Digital system design methodology Design flow Finite precision arithmetic libraries

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Implementation of DSP Systems Course Seminar

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  1. Implementation of DSP Systems Course Seminar ECE Department Tehran University Spring 2005

  2. A Practical Example Of DSP System Design, ADSL Modem DMT Engine DSP Systems Implementation

  3. Outline • A glance at ADSL modems structure • Digital system design methodology • Design flow • Finite precision arithmetic libraries • ADSL modulator/demodulator design • ADSL time equalizer design DSP Systems Implementation

  4. A Glance At ADSL Modems StructureADSL Modem Modulation • Discrete Multi Tone (DMT) modulation • Simple digital implementation by FFT, IFFT • Uses FDM • 256 sub-channels • QAM in all channels • Simultaneous voice Transmission DSP Systems Implementation

  5. A Glance At ADSL Modems StructureADSL Modem Block Diagram • ADSL DMT engine block diagram DSP Systems Implementation

  6. Digital System Design MethodologyDesign Flow- All Steps Together • General methodology • Much human brain work • Less automatic procedures • Test & verification importance DSP Systems Implementation

  7. Digital System Design MethodologyDesign Flow Step One: Simulation • High precision modeling • Using C or MATLAB • Converting high level protocol Or standard to A software model • System environment modeling • Engineering modeling • Quantization noise and other Finite precision effects modeling • Parametric modeling to find noise-parameter(s) relations • Wide simulation and parameter extraction DSP Systems Implementation

  8. Digital System Design MethodologyDesign Flow Step One: Simulation- Important Notes • For high precision modeling: • “MATLAB” is preferred because of its friendly interfaces, ready modules and visual capabilities • “C” is preferred because of its high simulation speed • For none-ideal engineering modeling • Finite-precision-arithmetic libraries • Fixed-floating point support • Different round-off, saturation, … strategies support DSP Systems Implementation

  9. Digital System Design MethodologyDesign Flow Step One: Simulation- Important Notes • Common parameter extraction method • Finding (output error- parameter(s)) curves using the below scheme • Common output error Criterions: BER, SNR And MSE • Finding optimal point on the curve(s) to satisfy defined error conditions with the lowest possible cost DSP Systems Implementation

  10. Digital System Design MethodologyDesign Flow Step Two: Hardware Modeling • Golden model creation • For test purpose • Behavioral modeling • Component modeling • Interfacing considerations • Model synthesizability • Structural modeling • System modeling • Components wiring DSP Systems Implementation

  11. Digital System Design MethodologyDesign Flow Step Two: Hardware Modeling- Important Notes • Golden model creation • Simplifies test of the final model • Functionally same as C or MATLAB model • Not necessarily synthesizable or efficient • Component modeling • Common design strategy: top-down design, bottom-up wiring • Extracted parameters from simulation step, inserted into components DSP Systems Implementation

  12. Digital System Design MethodologyDesign Flow Step Three: Implementation • FPGA implementation • FPGA specific HDL languages such as AHDL • Usually better performance when lower level components described @ RTL level • Hardware emulation systems • ASIC implementation DSP Systems Implementation

  13. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • C language does not have sufficient capabilities needed for bit-true modeling • Special libraries need to be developed that support • Different finite-length number representations (fixed, float,…) • Different finite-length sign representations (2’s complement, sign and magnitude, …) • Basic arithmetic operations with finite precision (sum, sub,…) • Different round-off strategies (truncation, rounding,…) • Different overflow strategies (maximum saturation, zero saturation, wrap around,…) DSP Systems Implementation

  14. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • Using the libraries, the system should be modeled and simulated with different library options • All trade-offs and strategies can be extracted • Number representation method (fixed, float, …) • Sign representation • Round-off strategy • Overflow strategy • Each trade-off or strategy corresponds to A different hardware implementation DSP Systems Implementation

  15. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • “ACOLADE” library • Written in c language • Parameters • Word_width (fixed or float selection) • Precision (precision selection) • RND_CHR (round-off strategy) • OVL_CHR (overflow strategy) DSP Systems Implementation

  16. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • CFinite Length Arithmetic Modeling Extension, C_FLAME library • Developed in UT SI lab • Supports different truncation and rounding round-off strategies • Supports sum, sub and multiply arithmetic operations • Library interface functions: dec2bin, bin2dec • Negation function: negate DSP Systems Implementation

  17. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • CFinite Length Arithmetic Modeling Extension, C_FLAME library • Arithmetic functions • Fixed point • Scaling functions: sum, sub, sum_wa, multiply • Saturation functions: sum_sat, sub_sat, sub_wa • Block floating point • Sum_bfp, sub_bfp DSP Systems Implementation

  18. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • C_FLAME library data structure • High precision input data for library must be scaled, -1≤ inputs < 1 • Fixed point is aligned after the most significant bit of the numbers (MSB of each number, represents sign) • High precision scaled input data should be converted to finite precision data for C_FLAME functions by library interface functions DSP Systems Implementation

  19. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • C_FLAME library data structure (Cntd.) • Inside C_FLAME, all binary finite precision numbers treated as integer numbers • Numbers representation inside C_FLAME Struct binary{ long int number; Int length;} DSP Systems Implementation

  20. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • Different C_FLAME summation functions • Saturated fixed point summation • Void sum_sat (binary a, binary b, binary *k) • Scaling fixed point summation • Void sum (int round_truncate, binary a, binary b, Int resultlength, binary *k) • Block floating point summation • Void sum_bfp(int round_truncate, binary a, binary b, int resultlength, binary *k) • Wrap around summation • Void sum_wa(binary a, binary b, binary *k); DSP Systems Implementation

  21. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • Illustration of functionality of different add functions in C_FLAME library • Sum_sat function • Output length=input length • No round-off strategy needed • When not overflow The function returns result(n-1 ,0) • When overflow The function saturates and returns Maximum and minimum representable numbers DSP Systems Implementation

  22. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • Illustration of functionality of different add functions in C_FLAME library • Sum function • If output length=input length +1 Function returns (C & result(n-1,0)) Round-off strategy not needed • If output length= input length Function returns (C & result(n-1,1)) Considering round-off strategy DSP Systems Implementation

  23. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • Illustration of functionality of different add functions in C_FLAME library • Sum_bfp function • If output length=input length +1 Function returns (C & result(n-1,0)) Round-off strategy not needed • If output length= input length • When not overflow Function returns (result(n-1,0)) • When overflow Function returns (C & result(n-1,1)) DSP Systems Implementation

  24. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • Illustration of functionality of different add functions in C_FLAME library • Sum_wa function • Output length=input length • No round-off strategy needed • No saturation strategy DSP Systems Implementation

  25. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • A finite precision complex multiply Finite_precision_complex_multiply (double: ra,ia,rb,ib, int r_t) { Struct binary: rab,iab,rbb,ibb,partialmul1,partialmul2; dec2bin(ra,8,rab); Dec2bin(ia,8,iab); Dec2bin(rb,8,rbb);//converting high precision inputs to finite precision Dec2bin(ib,8,ibb); Multiply(r_t , rab , rbb , 8 , &partialmul1); Multiply(r_t , iab , ibb , 8 , &partialmul2); Sub(r_t , partialmul1 , partialmul2 , 9 , &resultreal); Multiply(r_t , rab , ibb , 8 , &partialmul1); Multiply(r_t , iab , rbb , 8 , &partialmul2); Sum(r_t , partialmul1 , partialmul2 , 9 , &resultimag); Realpart=bin2dec(resultreal); imagpart=bin2dec(resultimag);} DSP Systems Implementation

  26. Digital System Design MethodologyFinite-Precision-Arithmetic Libraries • Block floating point • Needs extra hardware • A solution between fixed and floating point • Wide range representation capability • Simple hardware implementation • Low quantization noise sensitivity • Low delay DSP Systems Implementation

  27. Digital System Design MethodologyADSL Modulator/Demodulator Design • IFFT/FFT used for modulation/demodulation • The most complicated and most important block of an ADSL modem • Hardware structure • Operation count • Quantization noise • Design constraints (speed, area, power) DSP Systems Implementation

  28. Digital System Design MethodologyADSL Mo/Dem- Implementation Method Selection Space • A multi-dimensional space • Different algorithms • Radix 2, radix 4, radix 8, split radix, mixed radix • Different algorithm versions • Decimation in time (DIT), decimation in frequency (DIF) • Different butterfly structures • Symmetric structures, asymmetric structures • Different implementations • Full parallel structure, column structure, FFT processor structure, pipeline structure DSP Systems Implementation

  29. Digital System Design MethodologyADSL Mo/Dem- Choosing Suitable Structure • Selection criteria • Maximum delay constraint (250 µs) • Hardware cost (# of adders, multipliers,…) • Maximum acceptable quantization noise • Implementation complexity (VLSI layout,…) DSP Systems Implementation

  30. Word Length=12 0.16 Word Length=16 0.04 0.15 0.14 0.03 Error 0.13 Error 0.02 0.12 0.01 0.11 8 10 12 14 16 Constant Length 0 8 10 12 14 16 Constant Length Digital System Design MethodologyADSL Mo/Dem- FFT Block C Simulation Results • Change of “output error” due to increase of “coefficient length” DSP Systems Implementation

  31. Constant Length=12 20 15 Error 10 Constant Length=16 20 5 15 0 8 10 12 14 16 Error Word Length 10 5 0 8 10 12 14 16 Word Length Digital System Design MethodologyADSL Mo/Dem- FFT Block C Simulation Results • Change of “output error” due to increase of “word length” DSP Systems Implementation

  32. Constant Length=8 16 14 12 Constant Length=16 10 16 Truncation Error 8 14 6 12 4 10 Rounding Truncation 2 Error 8 0 8 9 10 11 12 13 14 15 16 6 Word Length 4 Rounding 2 0 8 9 10 11 12 13 14 15 16 Word Length Digital System Design MethodologyADSL Mo/Dem- FFT Block C Simulation Results • Change of “output error” due to using “rounding” instead of “truncation” DSP Systems Implementation

  33. Digital System Design MethodologyADSL Mo/Dem- Components Implementation • Enhanced multipliers to do biased rounding instead of truncation DSP Systems Implementation

  34. Digital System Design MethodologyADSL Mo/Dem- Components Implementation • Enhanced adders/subtractors to do unbiased rounding instead of truncation on output DSP Systems Implementation

  35. Digital System Design MethodologyADSL Time Equalizer Design • A digital filter to cancel line distortion • Implemented as A 16 tap adaptive FIR filter (changeable coefficients) DSP Systems Implementation

  36. Digital System Design MethodologyADSL Time Equalizer - Choosing A Suitable Structure • Constant length = filter word length • Selection criteria • Maximum delay constraint • Hardware cost (# of adders, multipliers, …) DSP Systems Implementation

  37. FIR Filter Output Error 0 . 045 0 . 04 0 . 035 0 . 03 Error 0 . 025 0 . 02 0 . 015 0 . 01 0 . 005 0 8 9 10 11 12 13 14 15 16 Word Length Digital System Design MethodologyADSL Time Equalizer – TEq C Simulation Results • Change of “output error” due to increase of “word length” • Output error is Negligible with Respect to FFT DSP Systems Implementation

  38. FIR Filter Output Error 0.045 0.04 0.035 0.03 Error 0.025 Truncating 0.02 0.015 0.01 Rounding 0.005 0 8 9 10 11 12 13 14 15 16 Word-Length Digital System Design MethodologyADSL Time Equalizer – TEq C Simulation Results • Change of “output error” due to using “rounding” instead of “truncation” DSP Systems Implementation

  39. References • A.V. Oppenheim, R.W. Shafer, “Discrete-time Signal Processing”, Englewood Cliffs: New Jersey, Prentice-Hall Inc., 1999. • V.K. Madisetti, D.B. Williams, “The Digital Signal Processing Handbook”, Florida: CRC-Press, 1998. • Shousheng He, Mats Torkelson, “Design and Implementation of a 1024 Point FFT Processor”, IEEE Custom Integrated Circuits Conference, 1998. • Acolade Library Reference Manual DSP Systems Implementation

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