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State Machine Timing Techniques for Improved Latencies and Clock Timings

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baylis
15 diapositives · 262 Views · Jan 04, 2020

Learn about retiming in state machines to balance latencies, accelerate or retard cycles, and improve clock timings. Understand the concepts of pipelining and the effects of synchronizers on outputs. Topics include Moore vs. Mealy machines, vending machine examples, and pipelining principles.

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State Machine Timing Techniques for Improved Latencies and Clock Timings
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  1. State Machine Timing • Retiming • Slosh logic between registers to balance latencies and improve clock timings • Accelerate or retard cycle in which outputs are asserted • Pipelining • Splitting computations into overlapped, smaller time steps CS 150 - Fall 2005 – Lec #16 – Retiming - 1

  2. Recall: Synchronous Mealy Machine Discussion • Placement of flipflops before and after the output logic changes the timing of when the output signals are asserted … Synchronizer Circuitry at Inputs and Outputs CS 150 - Fall 2005 – Lec #16 – Retiming - 2

  3. Recall: Synchronous Mealy Machine withSynchronizers Following Outputs Case III: Synchronized Outputs Signal goes into effect one cycle later A asserted during Cycle 0, ƒ' asserted in next cycle Effect of ƒ delayed one cycle CS 150 - Fall 2005 – Lec #16 – Retiming - 3

  4. N’ D’ + Reset (N’ D’ + Reset)/0 Reset Reset/0 0¢ [0] 0¢ N’ D’ N’ D’/0 N N/0 5¢ [0] 5¢ D D/0 N’ D’ N’ D’/0 N N/0 10¢ [0] 10¢ N’ D’ N’ D’/0 D D/1 N+D N+D/1 15¢ [1] 15¢ Reset’ Reset’/1 Vending Machine State Machine • Mealy machine • outputs associated with transitions • Moore machine • outputs associated with state CS 150 - Fall 2005 – Lec #16 – Retiming - 4

  5. State Machine Retiming • Moore vs. (Async) Mealy Machine • Vending Machine Example Open asserted only whenin state 15 Open asserted when lastcoin inserted leading tostate 15 CS 150 - Fall 2005 – Lec #16 – Retiming - 5

  6. State Machine Retiming • Retiming the Moore Machine: Faster generation of outputs • Synchronizing the Mealy Machine: Add a FF, delaying the output • These two implementations have identical timing behavior Push the AND gate through theState FFs and synchronize withan output FF Like computing open in the priorstate and delaying it one state time CS 150 - Fall 2005 – Lec #16 – Retiming - 6

  7. State Out prop delay Open Retimed Open Out calc Plus set-up Open Calculation NOTE: overlaps with Next State calculation State Machine Retiming • Effect on timing of Open Signal (Moore Case) Clk FF prop delay CS 150 - Fall 2005 – Lec #16 – Retiming - 7

  8. FF input in retimed Moore implementation FF input in synchronous Mealy implementation State Machine Retiming • Timing behavior is the same, but are the implementations really identical? Only differencein don’t care caseof nickel and dimeat the same time CS 150 - Fall 2005 – Lec #16 – Retiming - 8

  9. Pipelining review from CS61C: Analog to washing clothes: step 1: wash (20 minutes) step 2: dry (20 minutes) step 3: fold (20 minutes) 60 minutes x 4 loads  4 hours wash load1 load2 load3 load4 dry load1 load2 load3 load4 fold load1 load2 load3 load4 20 min overlapped  2 hours Pipelining Principle CS 150 - Fall 2005 – Lec #16 – Retiming - 9

  10. wash load1 load2 load3 load4 dry load1 load2 load3 load4 fold load1 load2 load3 load4 Increase number of loads, average time per load approaches 20 minutes Latency (time from start to end) for one load = 60 min Throughput = 3 loads/hour Pipelined throughput  # of pipe stages x un-pipelined throughput. Pipelining CS 150 - Fall 2005 – Lec #16 – Retiming - 10

  11. General principle: Cut the CL block into pieces (stages) and separate with registers: T’ = 4 ns + 1 ns + 4 ns +1 ns = 10 ns F = 1/(4 ns +1 ns) = 200 MHz CL block produces a new result every 5 ns instead of every 9 ns Pipelining Assume T = 8 ns TFF(setup +clkq) = 1 ns F = 1/9 ns = 111 MHz Assume T1 = T2 = 4 ns CS 150 - Fall 2005 – Lec #16 – Retiming - 11

  12. Without FF overhead, throughput improvement proportional to # of stages After many stages are added. FF overhead begins to dominate: Other limiters to effective pipelining: Clock skew contributes to clock overhead Unequal stages FFs dominate cost Clock distribution power consumption feedback (dependencies between loop iterations) Limits on Pipelining FF “overhead” is the setup and clk to Q times. CS 150 - Fall 2005 – Lec #16 – Retiming - 12

  13. F(x) = yi = a xi2 + b xi + c x and y are assumed to be “streams” Divide into 3 (nearly) equal stages. Insert pipeline registers at dashed lines. Can we pipeline basic operators? Computation graph: Pipelining Example CS 150 - Fall 2005 – Lec #16 – Retiming - 13

  14. Example: Pipelined Adder • Possible, but usually not done … (arithmetic units can often be made sufficiently fast without internal pipelining) CS 150 - Fall 2005 – Lec #16 – Retiming - 14

  15. State Machine Retiming Summary • Retiming • Vending Machine Example • Very simple output function in this particular case • But if output takes a long time to compute vs. the next state computation time -- can use retiming to “balance” these calculations and reduce the cycle time • Pipelining • Introduce registers to split computation to reduce cycle time and allow parallel computation • Trade latency (number of stage delays) for cycle time reduction CS 150 - Fall 2005 – Lec #16 – Retiming - 15