ECE 667Spring 2013Synthesis and Verificationof Digital Systems Binary Decision Diagrams (BDD)
Outline • Background • Canonical representations • BDD’s • Reduction rules • Construction of BDD’s • Logic manipulation of BDD’s • Application to verification and SAT • Reading: read one of the BDD tutorials available on class web site • Anderson, or • Somenzi ECE 667 Synthesis & Verification - BDD
Common Representations • Boolean functions ( f : B B ) • Truth table, Karnaugh map • SoP, PoS, ESoP • Reed-Muller expansions (XOR-based) • Decision diagrams (BDD, ZDD, etc.) • Each minimal, canonical representation is characterized by • Decomposition type • Shannon, Davio, moment decomposition, Taylor exp., etc. • Reduction rules • Redundant nodes, isomorphic sub-graphs, etc. • Composition method (“Apply”, compose rule) • What they represent • Boolean functions (f : B B) • Arithmetic functions (f : B Int ) • Algebraic expressions (f : Int Int ) ECE 667 Synthesis & Verification - BDD
Binary Decision Diagrams (BDD) • Based on recursive Shannon expansion f = x fx + x’ fx’ • Compact data structure for Boolean logic • can represents sets of objects (states) encoded as Boolean functions • Canonical representation • reduced ordered BDDs (ROBDD) are canonical • essential for verification ECE 667 Synthesis & Verification - BDD
ROBDD’s • Directed acyclic graph (DAG) • One root node, two terminal nodes 0, 1 (sinks) • Each node has exactly two children, associated with a variable • Shannon co-factoring tree, except reduced and ordered (ROBDD) • Reduced: • any node with two identical children is removed • two nodes with isomorphic BDD’s are merged • Ordered: • Co-factoring variables (splitting variables) always follow the same order along all paths xi1 < xi2 < xi3 < … < xin ECE 667 Synthesis & Verification - BDD
Root node a a c+bd b c c+bd b b d*b c+d c d c c b b d d 0 1 0 1 BDD Example Two different orderings, same function. f = ab+a’c+bc’d 1 0 ECE 667 Synthesis & Verification - BDD
Notreduced ! a a c c c b b b c 1 1 0 0 ROBDD Ordered BDD (OBDD): Input variables are ordered - each path from root to sink visits nodes with labels (variables) in the same order. not ordered ordered {a,c,b} Reduced Ordered BDD (ROBDD) - reduction rules: • if the two children of a node are the same, the node is eliminated: f = v f + v’ f • if two nodes have isomorphic graphs, they are replaced by one of them These two rules make it so that each node represents a distinct logic function. ECE 667 Synthesis & Verification - BDD
f v 0 1 fv fv Efficient Implementation of BDD’s • BDDs is a compressed Shannon co-factoring tree: • f = v fv + v fv • leafs are constants “0” and “1” • Three components make ROBDDs canonical (Proof: Bryant 1986): • unique nodes for constant “0” and “1” • identical order along each path • hash table that ensures: • (node(fv) = node(gv)) Ù (node(fv) = node(gv)) Þ node(f) = node(g) • provides recursive argument that node(f) is unique when using the unique hash-table ECE 667 Synthesis & Verification - BDD
Onset is Given by all Paths to “1” F = b’+a’c’ = ab’+a’cb’+a’c’BDD encodesall paths to the 1 node Notes: • By tracing paths to the 1 node, we get a cover of pairwise disjoint cubes. • The power of the BDD representation is that it does not explicitly enumerate all paths; rather it represents paths by a graph whose size is measured by the number of the nodes, and not paths. • A DAG can represent an exponential number of paths with a linear size (number of nodes) in terms of its variables. • BDDs can be used to efficiently represent sets • interpret elements of the onset as elements of the set • f is called the characteristic function of that set f a 0 1 fa = cb’+c’ c 1 fa= b’ b 0 0 1 0 1 ECE 667 Synthesis & Verification - BDD
b is top variable of f f a f b reduced b 0 1 0 1 v is top variable of f f f v 1 0 MUX v 0 1 g h g h Implementation • Variables are totally ordered: If v < w then v occurs “higher” up in the ROBDD Top variable of a function f is a variable associated with its root node. Reduction (redundant node) fa = b, fa = b f does not depend on a sincefa = fa . • Each node is written as a triple: f = (v,g,h), where g = fv and h = fv . We read this triple as: f = if v then g else h = ite (v,g,h) = vg+v ’ h ECE 667 Synthesis & Verification - BDD
f = ac + bc f 1 edge a b c f 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 0 edge a b b c c c c 0 0 0 0 0 1 1 1 Truth table Decision tree BDD Construction – naïve way • Reduced Ordered BDD ECE 667 Synthesis & Verification - BDD
f a f = a g(b) + a’ g(b) = g(b) g g b b BDD Reduction Rules -1 • Eliminate redundant nodes (with both edges pointing to same node) ECE 667 Synthesis & Verification - BDD
f f1 f2 a a a h g h g b c b c f1 = fa’ g(b) + fa h(c) = f2 f = f1 = f2 BDD Reduction Rules -2 • Merge duplicate nodes (isomorphic subgraphs) • Nodes must be unique ECE 667 Synthesis & Verification - BDD
f f f = (a+b)c a a a b b b b b c c c c c c c 0 0 0 1 1 1 • 2. Merge duplicate nodes 3. Remove redundant nodes 1. Merge terminal nodes BDD Construction – cont’d ECE 667 Synthesis & Verification - BDD
BDD Construction – the right way f = (a + b) c ECE 667 Synthesis & Verification - BDD
F F’ ¬ • Complement ¬ F = F’ • (switch the terminal nodes) F(y) F(y) F(x,y) F(x,y) Restrict Restrict x=b x=b 0 0 0 0 0 1 1 1 0 1 1 1 Logic Manipulation using BDDs Useful operators • Complement ¬ F = F’ • (switch the terminal nodes) • Restrict: F|x=b = F(x=b)where b = const • Restrict: F|x=b = F(x=b)where b = const • To restrict variable x to 1, reconnect all incoming edges to nodes x to their1-nodes • To restrict variable x to 0, reconnect all incoming edges to nodes x to their0-nodes • To restrict variable x to 1, reconnect all incoming edges to nodes x to their1-nodes • To restrict variable x to 0, reconnect all incoming edges to nodes x to their0-nodes ECE 667 Synthesis & Verification - BDD
a a a d c d d b b b b b b b c c c 0 0 0 0 1 1 1 1 Restrict Operator ( f (c=0, d=1) ) f = (a+d)(b+c)+a’d’bc fc’ = (a+d)b fc’d= (a+1)b = b fc’d = b Original BDD • Set c = 0 • Set d = 1 Restricted BDD ECE 667 Synthesis & Verification - BDD
Useful BDD Operators – Apply Operation • Basic operator for efficient BDD manipulation (structural) • Based on recursive Shannon expansion F <op> G = x (Fx<op> Gx) + x’(Fx’<op> Gx’) where<op> = binary operations: OR, AND, XOR, etc ECE 667 Synthesis & Verification - BDD
F G G F = 0 0 1 1 0 1 APPLY Operator • Useful in constructing BDD for arbitrary Boolean logic • Any logic operation can be expressed using Apply (ITE) • Efficient algorithms, work directly on BDD graphs • Apply: F G, any Boolean operation (AND, OR, XOR, ) ECE 667 Synthesis & Verification - BDD
F G G F = 0 0 1 1 0 1 Apply Operation (cont’d) • Apply: F G where stands for any Boolean operator (AND, OR, XOR, etc) • Apply: F G where stands for any Boolean operator (AND, OR, XOR, etc) • Any logic operation can be expressed using only Restrict and Apply • Efficient algorithms, work directly on BDDs • Apply can be used to construct a BDD bottom-up • From primary inputs, through internal logic gates, to output ECE 667 Synthesis & Verification - BDD
a AND c ac a 2 a a = = c 3 1.3 2.3 AND c c 03 10 0 0 0 11 1 1 1 Apply Operation - AND • F G = x (FxGx) + x’(Fx’Gx’) ECE 667 Synthesis & Verification - BDD
ac f = ac+bc bc 4 a 6 b a a OR b 5 7 = = b 4+6 7+5 0+6 0+7 0+5 6+5 c c c c 0+0 0 0 0 0 1 1 1 1 Apply Operation - OR • F + G = x (Fx+Gx) + x’(Fx’+Gx’) ECE 667 Synthesis & Verification - BDD
a a F = a’bc + abc +ab’c G = ac +bc b b c c 0 0 1 1 Application to Verification • Equivalence Checking of combinational circuits • Canonicity property of BDDs: • if F and G are equivalent, their BDDs are identical (for the same ordering of variables) ECE 667 Synthesis & Verification - BDD
H a ab b c 1 0 ab’c Application to SAT • Functional test generation • SAT, Boolean satisfiability analysis • to test for H = 1 (0), find a path in the BDD to terminal 1 (0) • the path, expressed infunction variables, gives a satisfying solution (test vector) • Problem: size explosion ECE 667 Synthesis & Verification - BDD
Efficient Implementation of BDD’s Unique Table: key = (v,G,H), where F = ITE(v,G,H). • avoids duplication of existing nodes • Hash-Table: hash-function(key) = value • identical to the use of a hash-table in AND/INVERTER circuits hash value of key collision chain • Computed Table: key = (F,G,H) • avoids re-computation of existing results hash value of key No collision chain ECE 667 Synthesis & Verification - BDD
Unique Table - Hash Table • Before a node (v, g, h ) is added to BDD data base, it is looked up in the “unique-table”. If it is there, then existing pointer to node is used to represent the logic function. Otherwise, a new node is added to the unique-table and the new pointer returned. • Thus a strong canonical form is maintained. The node for f = (v, g, h ) exists iff(v, g, h ) is in the unique-table. There is only one pointer for (v, g, h ) and that is the address to the unique-table entry. • Unique-table allows single multi-rooted DAG to represent all users’ functions: hash index of key collision chain ECE 667 Synthesis & Verification - BDD
Computed Table Keep a record of (F, G, H ) triplets already computed by the ITE operator • software cache ( “cache” table) • simply hash-table without collision chain (lossy cache) ECE 667 Synthesis & Verification - BDD
G G two different DAGs 0 1 0 1 G G only one DAG using complement pointer 0 1 Extension - Complement Edges Combine inverted functions by using complemented edge • similar to circuit case • reduces memory requirements • BUT MORE IMPORTANT: • makes some operations more efficient (NOT, ITE) ECE 667 Synthesis & Verification - BDD
V V V V V V V V Extension - Complement Edges To maintain strong canonical form, need to resolve 4 equivalences: Solution: Always choose one on left, i.e. the “then” leg must have no complement edge. ECE 667 Synthesis & Verification - BDD
