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ECE 667 Synthesis and Verification of Digital Systems

Formal Verification Combinational Equivalence Checking. ECE 667 Synthesis and Verification of Digital Systems. Out. In. CL. PI. Po. CL. Ps. Ns. R. Equivalence Checking. Two circuits are functionally equivalent if they exhibit the same behavior Combinational circuits

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ECE 667 Synthesis and Verification of Digital Systems

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  1. Formal Verification Combinational Equivalence Checking ECE 667Synthesis and Verificationof Digital Systems ECE 667 - Synthesis & Verification

  2. ECE 667 - Synthesis & Verification Out In CL PI Po CL Ps Ns R Equivalence Checking • Two circuits are functionally equivalent if they exhibit the same behavior • Combinational circuits • for all possible input values • Sequential circuits • for all possible input sequences

  3. ECE 667 - Synthesis & Verification Architectural Specification (informal) Test Programs Cycle Simulation RTL Specification (Verilog, VHDL) Equivalence Checking Circuit Implementation (Gate level) Circuit Simulation Layout Implementation (GDS II) Application of EC in Microprocessor Designs

  4. ECE 667 - Synthesis & Verification RTL Specification Cell-Based Synthesis Equivalence Checking Standard Cell Implementation Engineering Changes (ECOs) Equivalence Checking Final Implementation Application of EC in ASIC Designs

  5. ECE 667 - Synthesis & Verification Combinational Equivalence Checking • Functional Approach • transform output functions of combinational circuits into a unique (canonical) representation • two circuits are equivalent if their representations are identical • efficient canonical representation: BDD, BMD, etc. • Structural • identify structurally similar internal points • prove internal points (cut-points) equivalent • find implications

  6. ECE 667 - Synthesis & Verification Functional Equivalence • Circuits for which BDD can be constructed • represent multi-output circuits as shared BDDs • BDDs must be identical (for the same variable ordering) • Circuits whose BDDs are too large • cannot construct BDDs, memory problem • use partitioned BDD method • decompose circuit into smaller pieces, each as BDD • check equivalence of internal points (cut-point method)

  7. ECE 667 - Synthesis & Verification Degree of Structural Difference Structure- independent techniques Combined methods Structural techniques Size EC Methods Structure-independent techniques: • exhaustive simulation • decision diagrams (*DD*) Structural techniques: • graph hashing • SAT solvers including learning techniques

  8. ECE 667 - Synthesis & Verification F G g2 f2 z z g1 f1 y y x x Functional (structure-independent) Methods • Decompose each function into functional blocks • represent each block as a BDD (partitionedBDD method) • define cut-points (z) • verify equivalence of blocks at cut-points starting at primary inputs

  9. ECE 667 - Synthesis & Verification v1 f1 f3 f2 v2 0? 0? x 0? v1 f1 f3 f2 v2 Cut-point based EC Cut-points are used to partition the Miter Cut-point guessing: • Compute net signature with random simulator • Sort signatures + select cut-points • Iteratively verify and refine cut-points • Verify outputs

  10. ECE 667 - Synthesis & Verification F G g2 f2 z1 z2 g1 f1 y y x x Cut-Points Resolution Problem • If all pairs of cut-points (z1,z2) are equivalent • so are the two functions, F,G • If intermediate functions (f2,g2) are not equivalent • the functions (F,G) may still be equivalent • this is called false negative • Why do we have false negative ? • functions are represented in terms of intermediate variables • to prove/disprove equivalence must represent the functions in terms of primary inputs (BDD composition)

  11. ECE 667 - Synthesis & Verification F G g2 f2 z z g1 f1 y y x x Cut-Point Resolution – Theory • Let f1(x)=g1(x)x • if f2(z,y)  g2(z,y), z,y then f2(f1(x),y)  g2(f1(x),y)  F  G • if f2(z,y) g2(z,y), z,yf2(f1(x),y)  g2(f1(x),y)  F  G We cannot say ifF  G or not • False negative • two functions are equivalent, but the verification algorithm declares them as different.

  12. ECE 667 - Synthesis & Verification 0, F  G (false negative) 1, F  G (true negative) F G Cut-Point Resolution – cont’d • How to verify if negative is false or true ? • Procedure 1: create a miter (XOR) between two potentially equivalent nodes/functions • perform ATPG test for stuck-at 0 • find test pattern to prove F  G • efficient for true negative (gives test vector, a proof) • inefficient when there is no test

  13. ECE 667 - Synthesis & Verification , F  G (false negative) FG = G F = Non-empty, F  G  Cut-Point Resolution – cont’d • Procedure 2: create a BDD for FG • perform satisfiability analysis (SAT) of the BDD • if BDD for FG = , problem is not satisfiable, false negative • BDD for FG, problem is satisfiable, true negative Note: must compose BDDs until they are equivalent, or expressed in terms of primary inputs • the SAT solution, if exists, provides a test vector (proof of non-equivalence) – as in ATPG • unlike the ATPG technique, it is effective for false negative (the BDD is empty!)

  14. ECE 667 - Synthesis & Verification d1 d2 a F G a • • b b c Structural Equivalence Check • Given two circuits, each with its own structure • identify “similar” internal points, cut sets • exploit internal equivalences • False negative problem may arise • F  G, but differ structurally (different local support) • verification algorithm declares F,G as different • Solution: use BDD-based or ATPG-based methods to resolve the problem. Also: implication, learning techniques.

  15. ECE 667 - Synthesis & Verification d=0 b=x d=x b=x f=0 f=1 a=1 a=0 c=x e=0 c=x e=x Implication Techniques • Techniques that extract and exploit internal correspondences to speed up verification • Implications – direct and indirect Direct: a=1f=0 Indirect (learning): f=1a=0

  16. ECE 667 - Synthesis & Verification G H a a a H b b b G=1 c 0 1 0 1 Learning Techniques • Learning • process of deriving indirect implications • Recursive learning • recursively analyzes effects of each justification • Functional learning • uses BDDs to learn indirect implications G=1 H=0

  17. ECE 667 - Synthesis & Verification a H b G=1 c Learning Techniques –cont’d • Other methods to check implications G=1 H=0 • Build a BDD for G • H’ • If this function is satisfiable, the implication holds and gives a test vector • Otherwise it does not hold • Since G=1 H=0  (G’+H’)=1, build a BDD for (G’+H’) • The implication holds if (G’+H’)=1 (tautology)

  18. ECE 667 - Synthesis & Verification Summary • Industrial EC checkers almost exclusively use a combinational EC paradigm • sequential EC is too complex, can only be applied to design with a few hundred state bits • combinational methods scale linearly with the design size for a given fixed size and “functional complexity” of the individual cones • Still, pure BDDs and plain SAT solvers cannot handle all logic cones • BDDs can be built for about 80% of the cones of high-speed designs • less for complex ASICs • plain SAT blows up on a “Miter” structure • Contemporary method highly exploit structural similarity of designs to be compared

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