Chapter 3 Arithmetic for Computers

# Chapter 3 Arithmetic for Computers

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## Chapter 3 Arithmetic for Computers

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1. Chapter 3Arithmetic for Computers 授課教師: 張傳育 博士 (Chuan-Yu Chang Ph.D.) E-mail: chuanyu@yuntech.edu.tw Tel: (05)5342601 ext. 4337

2. Introduction • 自然數字的二進位表示法 • 二進位與十進位的轉換(binary to decimal conversion) • 二進位與十六進位的轉換(binary to hexadecimal conversion) • 十六進位與十進位的轉換 • 負數表示法 • 二進位數的邏輯運算 (and, or) • 二進位數的算術運算(+, -, *, /) • 分數(fraction)及浮點表示法 • 硬體如何實際執行加、減、乘、除。

3. Signed and Unsigned Numbers • In any number base, the value of ith digit d is • Binary numbers (base 2)least significant bit: the rightmost bitmost significant bit: the leftmost bit 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001... decimal: 0...2n-1 • Of course it gets more complicated: numbers are finite (overflow) fractions and real numbers negative numbers e.g., no MIPS subi instruction; addi can add a negative number • How do we represent negative numbers? i.e., which bit patterns will represent which numbers?

4. Example: ASCII Vs. Binary Numbers • What is the expansion in storage if the number 1 billion is represented in ASCII versus a 32 bit integer? • 1 billion = 1000000000 (10個ASCII符號)1 ASCII = 8 bits所以需要8*10=80 bits因此80/32=2.5

5. Possible Representations of Negative Numbers Sign and Magnitude: One's Complement Two's Complement000 = +0 000 = +0 000 = +0 001 = +1 001 = +1 001 = +1 010 = +2 010 = +2 010 = +2 011 = +3 011 = +3 011 = +3100 = -0 100 = -3 100 = -4 101 = -1 101 = -2 101 = -3 110 = -2 110 = -1 110 = -2 111 = -3 111 = -0 111 = -1 • Issues: number of zeros, ease of operations • Which one is best? Why? • The drawbacks of the sign-magnitude representation: • It’s not obvious where to put the sign bit. • Adders for sign and magnitude may need an extra step to set the sign because we can’t know in advance what the proper sign will be. • Two zeros, positive and negative zero.

6. MIPS: 2’s complement maxint minint 以0為前導的數為正值 • 32 bit signed numbers:0000 0000 0000 0000 0000 0000 0000 0000two = 0ten0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten...0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten...1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten 以1為前導的數為負值

7. Example: Binary to Decimal conversion • What is the decimal value of this 32-bits two’s complement number?1111 1111 1111 1111 1111 1111 1111 1100(2)

8. Two's Complement Operations • Negating a two's complement number: invert all bits and add 1 • Converting n bit numbers into numbers with more than n bits: • MIPS 16 bit immediate gets converted to 32 bits for arithmetic • copy the most significant bit (the sign bit) into the other bits 0010 -> 0000 0010 1010 -> 1111 1010 • "sign extension" • lbu: load byte unsigned • lb: load byte

9. Signed versus Unsigned Comparison • MIPS offers two versions of the set on less than comparison • 有號數的若小於則設定(slt, slti): set on less than, set on less than immediate • 無號數的若小於則設定(sltu, sltiu): set on less than unsigned, set on less than immediate unsigned • 範例． • 假設暫存器 \$s0含有以下的二進位數 • 1111 1111 1111 1111 1111 1111 1111 1111 • 而暫存器 \$s1含有以下的二進位數 • 0000 0000 0000 0000 0000 0000 0000 0001 • 經由以下兩個指令運算後，暫存器 \$t0及 \$t1的值為何？ • slt \$t0, \$s0, \$s1 • sltu \$t1, \$s0, \$s1 • 解答\$s0: signed=-1, unsigned=4294967295 \$s1: signed=1, unsigned=1 • 得到 \$t0 = 1 及 \$t1 = 0.

10. Example : Negation Shortcut • Negate 2(10), and then check the result by negating -2(10). • 2(10) = 0000 0000 0000 0000 0000 0000 0000 0010 • Negating this number by inverting the bits and adding one.1111 1111 1111 1111 1111 1111 1111 1101 11111 1111 1111 1111 1111 1111 1111 1110= -2 • 0000 0000 0000 0000 0000 0000 0000 0001 10000 0000 0000 0000 0000 0000 0000 0010= 2 + 0變1，1變0 +

11. Example Sign Extension Shortcut • Convert 16-bit versions of 2 and -2 to 32-bit binary numbers. • The 16-bit binary version of the number 2 is2 = 0000 0000 0000 0010 • Macking 16 copies of the value in the most significant bit and placing that in the left-hand half of the word.0000 0000 0000 0000 0000 0000 0000 0010 • The 16-bit binary version of the number -2 is-2 = 11111111 1111 1110 • Macking 16 copies of the value in the most significant bit and placing that in the left-hand half of the word. 1111 1111 1111 1111 11111111 1111 1110

12. Binary-to-Hexadecimal Shortcut • Convert the following hexadecimal and binary numbers into the other base.(a) ECA8 6420(16)(b) 0001 0011 0101 0111 1001 1011 1101 1111(2) • E = 1110 0001 = 1C = 1100 0011 = 3A = 1010 0101 = 58 = 1000 0111 = 76 = 0110 1001 = 94 = 0100 1011 = B2 = 0010 1101 = D0 = 0000 1111 = F=>(a) 1110 1100 1010 1000 0110 0100 0010 0000=>(b) 13579BDF

13. Addition& Subtraction • Just like in elementary school (carry/borrow 1s)0111 0111 0110+0110 -0110 -0101110100010001 • Two's complement operations easy • subtraction using addition of negative numbersx – y = x + (-y) • Example: 0111-0110 = ?Solution: 0110=>1001+1=10100111 + 101010001

14. Addition& Subtraction (cont.) • Overflow (result too large for finite computer word): • e.g., adding two n-bit numbers does not yield an n-bit number 0111 +0001 note that overflow term is somewhat misleading, 1000 it does not mean a carry “overflowed”

15. Detecting Overflow • No overflow when adding a positive and a negative number • No overflow when signs are the same for subtraction • Overflow occurs when the value affects the sign: • overflow when adding two positives yields a negative • or, adding two negatives gives a positive • or, subtract a negative from a positive and get a negative • or, subtract a positive from a negative and get a positive • Effects of Overflow (2’s complement) • An exception (interrupt) occurs • Control jumps to predefined address for exception • Interrupted address is saved for possible resumption • MIPS has two kinds of arithmetic instructions to recognize the 2’s complement and unsigned integer. • add, addi, and sub cause exceptions on overflow. • addu, addiu, and subu do not cause exceptions on overflow.

16. Overflow conditions for addition and subtraction

17. Logical Operations 0 16 10 8 0 unused • Shifts • 邏輯左移指令 (sll) shift left logical： R形態格式 • 邏輯右移指令 (srl) shift right logical： R形態格式 • 範例：假如暫存器 \$s0內容為0000 0000 0000 0000 0000 0000 0000 1101而指令 sll \$t2, \$s0, 8 被執行\$t2的值將為多少？ • 解答0000 0000 0000 0000 0000 1101 0000 0000上述指令的機器語言為：sll \$t2, \$s0, 8

18. Logical Operations • bit-by-bit And (and) 指令 • and, andi • bit-by-bit Or (or) 指令 • Or, ori • Example: Mask (遮罩) • 如果暫存器 \$t2內含 • 0000 0000 0000 0000 0000 1101 0000 0000 • 而暫存器 \$t1內含 • 0000 0000 0000 0000 00111100 0000 0000 • 則在 MIPS 指令執行後 • and \$t0, \$t1, \$t2 #reg \$t0 = reg \$t1 & reg \$t2 • \$t0 的值將會是 • 0000 0000 0000 0000 00001100 0000 0000 • 在 MIPS 指令執行後 • or \$t0, \$t1, \$t2 #reg \$t0 = reg \$t1 | reg \$t2 • \$t0 的值將會是 • 0000 0000 0000 0000 0011 1101 0000 0000 5

19. Multiplication • More complicated than addition • accomplished via shifting and addition • More time and more area • Let's look at 3 versions based on grade school algorithm 0010 (multiplicand) __x_1011 (multiplier) • Negative numbers: convert and multiply • there are better techniques, we won’t look at them

20. First Version of the Multiplication Algorithm • 第一版乘法運算的演算法及硬體 • 乘積暫存器先預設為 0。 • 如果每個步驟須花費一個時脈週期， • 這一版的乘法運算就要花費100 • 個時脈週期才能完成。 • 相當於以手算方式進行，被乘數(multiplicand)每次往左移1bit，乘數(multiplier)每次往右移1bit。

21. Multiplication • Example: First Multiply Algorithm Fig 4.27

22. Second Version • 第二版乘法運算的演算法及硬體 • 32-位元ALU • 乘積暫存器先預設為 0。 • 在直式的乘法運算中，每次乘積均會產生一個部份積； • 因此，將目前的部份積左移一位，相當於將前一部份積往右移一位。 • 優點： • 只需右移電路。 • 被乘數暫存器只需32bit。 • ALU只需32bit。

23. Final Version • 優點： • 乘數暫存器併入乘積暫存器的右半段。 • 省掉multiplier暫存器及右移電路。

24. Example • 0010x0011

25. Multiplying Negative Numbers • Solution 1 • Convert to positive if required • Multiply as above • If signs were different, negate answer • Solution 2 • Booth’s algorithm

26. Comparison of Multiplication of Unsigned and Twos Complement Integer 部分積以2n bit表示 可解決被乘數為負值的問題，但若乘數為負值時，仍無解 0011 (+3)x 1001 (-7)00000011000000000000000011 . 00011011 (+27)

27. Booth’s algorithm ai-1 ai operation 0 0 1 1 0 1 0 1 Do nothing Add b Subtract b Do nothing • 令a為乘數(multiplier)，b為被乘數(multiplicand) • Booth’s algorithm的動作可表示成(ai-1-ai)其中上式值的意義如下：0 : do nothing+1 : add b-1 : subtract b • 將被乘數相對於乘積暫存器往左移，相當於乘以2的冪次方，因此Booth’s algorithm可寫成下式的乘積項和 • 將上式整理可得 • 而且a-1=0，因此(1)式可改寫成 a的2補數

28. Example: Booth’s Algorithm • 2*-3 = 0010 * 1101

29. Booth’s Algorithm

30. Examples Using Booth’s Algorithm

31. Examples Using Booth’s Algorithm (cont.)

32. Division • More complex than multiplication • Based on long division

33. Division of Unsigned Binary Integers Quotient 00001101 Divisor 1011 10010011 Dividend 1011 001110 Partial Remainders 1011 001111 1011 Remainder 100

34. First Version of the Division Algorithm • 每一次演算法需移動被除數往右1bit。 • 所以，將被除數放在64bit的左半部， • 餘數暫存器初值設為除數。

35. Example : First Divide Algorithm 初值是被除數的值 • Using a 4-bit version of the algorithm to calculate 7/2

36. Second version of the Division Algorithm • 第一版的除法器中， • 除數暫存器最多只有一半的位元是有用的，因此可將ALU寬度減半 • 將餘數左移一位元相當於將除數右移一位元

37. Third version of the Division Algorithm 餘數 商 • 藉由同時將運算元和商同時移位來加速除法運算。

38. Example : Third Divide Algorithm • Using a 4-bit version of the algorithm to calculate 7/2

39. Floating Point (a brief look) • We need a way to represent • numbers with fractions, e.g., 3.1416 • very small numbers, e.g., .000000001 • very large numbers, e.g., 3.15576 ´ 109 • Representation: • sign, exponent, significand: (–1)sign* significand * 2exponent • more bits for significand gives more accuracy • more bits for exponent increases range • IEEE 754 floating point standard: • single precision: 8 bit exponent, 23 bit significand • double precision: 11 bit exponent, 52 bit significand

40. Floating Point • +/- .significand x 2exponent • Point is actually fixed between sign bit and body of mantissa • There is one bit to the left of the radix point. • Exponent value is biased representation • A fixed value is subtracted from the field to get the true exponent value • The bias equals (2k-1-1) Biased Exponent Significand or Mantissa Sign bit

41. IEEE 754 floating-point standard • Leading “1” bit of significand is implicit • Exponent is “biased” to make sorting easier • all 0s is smallest exponent all 1s is largest • bias of 127 for single precision and 1023 for double precision • summary: (–1)sign* (1+significand) * 2exponent – bias • Example: • decimal: -.75 = -3/4 = -3/22 • binary: -.11 = -1.1 x 2-1 • floating point: exponent = 126 = 01111110 • IEEE single precision: 10111111010000000000000000000000

42. IEEE 754 Formats

43. IEEE 754 floating-point standard • Example: Show the IEEE 754 binary representation of the number -0.75 (10) in single and double precision • Solution:-0.75 = -(0.11)2 = -(1.1)2 * 2-1 single precision ：1 01111110 100000…0(126)10 double precision ：1 01111111110 1000 … 00000(1022)10

44. Example 1 • (a) Convert the decimal number -1.5 to a 32-bit floating-point number with IEEE 754 format.(b) Convert a 32-bits IEEE 754 format floating-point number 43A0C000 to the decimal number. • Solution: • (a) 1.5=1.12=1.1*20S=1, C=E+127=127=01111111, F=10000000000000000000000(b)43A0C000=0100 0011 1010 0000 1100 0000 0000 00002 S=0, C=10000111=135=E+127, =>E=8, F= 01000001100000000000 1.01000001102*28=101000001.12= 321.5

45. Example 2 • What decimal number is represented by this word? • Solution:符號位元為-1，指數欄位為129，有效數字欄位為1.01。

46. IEEE 754單精密度表示 • 指數值介於1到254之間 • -126~127 • 指數和假數都是0的情況，可視符號位元分成正零和負零。 • +0 : 0 00000000 00000000000000000000000 • -0 : 1 00000000 00000000000000000000000 • 指數全為1，假數全為0時，視符號位元代表正負無限大。 • +∞ : 0 11111111 00000000000000000000000 • -∞ : 1 11111111 00000000000000000000000 • 指數全為1，假數部分為非0，則表示Not a Number, NaN • 正規化的非零值： • (-1)s * 1.F * 2e-127

47. Example 3 • (a) What are the smallest negative number, largest negative number, smallest positive number and the largest positive number for 32 bit normalized floating-point number. • (b) What would be the range of exponential digit can represent in the IEEE 754 format? • Solution:(a)最小的指數為:-126最大的指數為:127最小的假數為:1.00000000000000000000000最大的假數為:1.11111111111111111111111所以最大正值:1.11111111111111111111111*2127最小正值:1.0*2-126最小負值:-1.11111111111111111111111*2127最大負值:- 1.0*2-126(b) -126~127

48. Floating-Point Arithmetic +/- • Floating-point arithmetic +/-的步驟 • Check for zeros • Align significands (adjusting exponents) • Add or subtract significands • Normalize result • Round the number

49. Example: • Assume that we can store four decimal digits of the significand and two decimal digits of the exponent. 9.999x101+1.610x10-1 • Step 1: 1.610 x 10-1=0.01610 x 101 • Step 2: Addition of the significands9.999 + 0.016 = 10.015 The sum is 10.015 x 101 • Step 3: Normalization10.015 x 101=1.0015 x 102 • Step 4: Round the number1.002 x 102

50. Floating-Point Addition • 浮點數加法運算 • 範例． • 試著將 0.5 和 -0.4375以二進位方式進行加法運算 • 解答． • 0.5 = (0.1)2 • = (1.0)2 * 2-1 • -0.4375 = - (0.0111)2 • = - (1.11)2 * 2-2 • 步驟 1. 比較兩個數的指數， 將指數大小調到與較大者相同： • - (1.11)2 * 2-2 = - (0.111)2 * 2-1 • 步驟 2. 將兩數之有效數字相加： • (1.0)2 * 2-1 - (0.111)2 * 2-1 = (0.001)2 * 2-1 • 步驟 3. 將總和正規化： • (0.001)2 * 2-1 = (1.0)2 * 2-4 • 步驟 4. 將結果四捨五入