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EE 4271 VLSI Design, Fall 2013

EE 4271 VLSI Design, Fall 2013. CMOS Combinational Gate. CMOS Combinational Circuits. Implementation of logic gates and other structures using CMOS technology. Basic element: transistor 2 types of transistors: n-channel (nMOS) and p-channel (pMOS)

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EE 4271 VLSI Design, Fall 2013

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  1. EE 4271 VLSI Design, Fall 2013 CMOS Combinational Gate

  2. CMOS Combinational Circuits • Implementation of logic gates and other structures using CMOS technology. • Basic element: transistor • 2 types of transistors: • n-channel (nMOS) and p-channel (pMOS) • Type depends on the semiconductor materials used to implement the transistor. • We want to model transistor behavior at the logic level in order to study the behavior of CMOS circuits  view pMOS and nMOS transistors as swithes. Combinational Logic

  3. CMOS transistors as Switches • 3 terminals in CMOS transistors: • G: Gate • D: Drain • S: Source nMOS transistor/switch X=1 switch closes (ON) X=0 switch opens (OFF) pMOS transistor/switch X=1 switch opens (OFF) X=0 switch closes (ON) Combinational Logic

  4. Networks of Switches • Use switches to create networks that represent CMOS logic circuits. • To implement a function F, create a network s.t. there is a path through the network whenever F=1 and no path when F=0. • Two basic structures: • Transistors in Series • Transistors in Parallel Combinational Logic

  5. Transistors in Series/Parallel nMOS in Series nMOS in Parallel a a a a Path between points a and b exists if bothX and Y are 1 X•Y Path between points a and b exists if eitherX or Y are 1 X+Y X X:X X Y X:X Y:Y Y Y:Y b b b b pMOS in Parallel pMOS in Series Path between points a and b exists if eitherX or Y are 0 X’+Y’ a a a a Path between points a and b exists if bothX and Y are 0 X’•Y’ X X:X’ X Y X:X Y:Y Y Y:Y’ b b b b Combinational Logic

  6. Networks of Switches (cont.) • In general: • nMOS in series is used to implement AND logic • pMOS in series is used to implement NOR logic • nMOS in parallel is used to implement OR logic • pMOS in parallel is used to implement NAND logic • Observe that: • 1 is the complement of 4, and vice-versa • 2 is the complement of 3, and vice-versa Combinational Logic

  7. +V X F = X’ GRD CMOS Inverter F = X’ X Logic symbol Transistor-level schematic • Operation: • X=1  nMOS switch conducts (pMOS is open) and draws from GRD  F=0 • X=0  pMOS switch conducts (nMOST is open) and draws from +V  F=1 Combinational Logic

  8. Fully Complementary CMOS NetworksBasic Gates Combinational Logic

  9. Fully Complementary CMOSComplex Gates Given a function F: • First take the complement of F to form F’ • Implement F’ as an nMOS net and connect it to GRD (pull-down net) and F. • Find dual of F’, implement it as a pMOS net and connect it to +V (pull-up net) and F. • Connect switch inputs. Combinational Logic

  10. Fully Complementary CMOS NetworksComplex Gates - Example F = (A+B)(A+C’) F’ = A’B’+A’C=A’(B’+C) Combinational Logic

  11. CMOS Transmission Gate (TG) Combinational Logic

  12. 2-input MUX Using CMOS TGs Combinational Logic

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