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EE 466/586 VLSI Design

EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University pande@eecs.wsu.edu. Lecture 7 Static MOS Gate Circuits. CMOS Gate Sizing. NAND and NOR gate sizing Follow board notes. Pseudo-NMOS Gate Sizing. Fanin and Fanout Considerations.

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EE 466/586 VLSI Design

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  1. EE 466/586VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu

  2. Lecture 7 Static MOS Gate Circuits

  3. CMOS Gate Sizing • NAND and NOR gate sizing • Follow board notes

  4. Pseudo-NMOS Gate Sizing

  5. Fanin and Fanout Considerations • Gates with a large number of inputs (high fan-in gates) • Too high resistance • Area penalty • Follow board notes • Fan Out • Output driving capability

  6. Fan Out

  7. VTC of NAND Gates • If input A is held high while input B switched from low to high, the gate is equivalent to an inverter with a 2W pull-up device and a 2W pull-down device. The resulting transfer characteristic would shift to the left of the standard inverter.

  8. VTC of NOR Gates

  9. Static Complementary CMOS VDD In1 • The function of the PUN is to provide a connection between the output and Vdd anytime the output of the logic gate is meant to be 1 • Similarly the role of the PDN is to connect the output to GND when the output is meant to be 0 PMOS only In2 PUN … InN F(In1,In2,…InN) In1 In2 PDN … NMOS only InN PUN and PDN are dual logic networks

  10. NMOS as PDN & PMOS as PUN • NMOS device can pull the output all the way down to GND, but the PMOS device can pull it down to Vtp • NMOS transmits a strong 0 • PMOS transmits a strong 1

  11. B A C D Complex CMOS Gate OUT = D + A • (B + C) A D B C

  12. Constructing a Complex Gate

  13. Sequential Logic 2 storage mechanisms • positive feedback A latch is level sensitive A register is edge-triggered • charge-based

  14. Latch versus Register • Register stores data when clock rises • Latch Stores data depending on the level of the clock D Q D Q Clk Clk Clk Clk D D Q Q

  15. Latches

  16. Latch-Based Design • N latch is transparentwhen f = 0 • P latch is transparent when f = 1 f N P Logic Latch Latch Logic

  17. Timing Definitions CLK Register t D Q t t su hold D DATA CLK STABLE t t c q 2 Q DATA STABLE t

  18. Timing Definitions • Tsu (Setup time) • Incoming data must be stable before the clock arrives • Thold (Hold time) • The length of time the data remains stable after the clock arrives for proper operation • If the data is stable before the setup time and continues to be stable after the hold time, the register will properly capture the data • Tclk-Q(clk to Q delay) • This is the delay from the time the clock arrives to the point at which the Q output stabilizes

  19. Maximum Clock Frequency tclk-Q + tp,comb + tsetup = T

  20. V Vi2 V V i o1 1 o 2 A C B V V = = V V i i 1 2 o o 1 2 Positive Feedback: Bi-Stability 1 1 o o V V 5 2 i V 1 A, B – Two stable operating points o V 5 2 i V

  21. Meta-Stability Gain should be larger than 1 in the transition region

  22. Cross-Coupled Pairs NOR-based set-reset

  23. Cross-Coupled NAND Added clock Cross-coupled NANDs This is not used in datapaths any more,but is a basic building memory cell

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