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Understanding Bessel Filters and Ground Loops in Signal Processing

In signal processing, it's crucial to analyze how filters like Bessel impact time responses, especially when dealing with signals that consist of numerous short pulses, such as those around 2 microseconds. Sampling at 20 microseconds can lead to information loss if pulse widths are not appropriately averaged. Ground loops can introduce communication issues among various components, affecting signal integrity. This text outlines the importance of time averaging, eliminating unnecessary gain boxes, and configuring analog processing chains for optimal signal detection.

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Understanding Bessel Filters and Ground Loops in Signal Processing

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Presentation Transcript

  1. False asymmetries/Ground Loops David Bowman 4/27/12

  2. Why do we need a filter? • The signal consists of a large number of pulses with widths of ~ 2 micro second • We sample at ~ 20 micro sec intervals (50 KHz rate) • It is necessary to form a time average of the signal to avoid loss of information because if the pulse width is less than the sampling interval, some pulsed don’t contribute

  3. Time response of different filters Time The desirable feature of the Bessel filter is that the time response does not have oscillations.

  4. Signal flow • Detector, preamp • TRIUMF adjustable gain module • Sum and difference and filter Amplifier • Ring sums and detector differences • VME 3 • ADC of Ring Sums, spin state and monitors • VME2 • ADC of detector differences • Different components are located in different crates and racks. • Communication by ground loops • Communication within Sum, Difference, and Filter box via ground loops and stray capicatance

  5. Ground loops If the loop is defined by conductors, E appears across the largest resistance

  6. Reconfigure analog signal processing chain • Eliminate TRIUMF gain box, Sum and difference box, Ring sums • Build new Bessel filter box with (gain of 3 -> gain of 6) connected to detector signals by twinex (shielded twisted pair) and connected to ADC’s in VME2 by twinex.

  7. Least bit ADC noise –staircase problem • is bin width, s is RMS noise on analog signal. • If s is ~ .5 G, average ADC signal ~ input signal • It is possible to achieve 6 V detector signal, and • s ~ .5 G.

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