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Designing an RFID Chip for Enhanced Shopping Experiences

This presentation outlines the development of an RFID chip aimed at meeting the increasing demand for efficient shopping solutions. Led by a team including Idongesit Ebong, Jenna Fu, Bowei Gai, Syed Hussain, and Jonathan Lee, under the guidance of Design Manager Myron Kwai, the project includes key phases such as architectural proposals, Verilog simulations, and advanced layout design. The presentation highlights the current status, discusses design decisions for improved performance, and addresses challenges related to size reduction and signal integrity.

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Designing an RFID Chip for Enhanced Shopping Experiences

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Presentation Transcript

  1. Presentation #9: Smart Cart 525 Idongesit Ebong (1-1)Jenna Fu (1-2)Bowei Gai (1-3)Syed Hussain (1-4)Jonathan Lee (1-5)Design Manager: Myron Kwai Overall Project Objective: Design a chip as part of a system that accommodates the growing demand for radio frequency identification (RFID) technology while creating a quicker, more convenient shopping experience. Stage IX: 16 Mar. 2005 Chip Level Layout

  2. Status • Design Proposal • Project chosen • Verilog obtained/modified • Architecture Proposal • Behavioral Verilog simulated • Size estimates/floorplanning • Gate-level implementation simulated in Verilog • Floorplan and more accurate transistor count • Schematic Design • Component Layout • Functional Block Layout • DRC of functional blocks • LVS of functional blocks • Chip Level Layout (98.56% Done) • 3 Main blocks (each block LVSes) • Full chip LVS • Simulations

  3. Design Decisions • Decided to route more wires over the SBOX and use metal 4 to reach registers on the right • Move items in the encryption block higher up and redesign SBOX logic

  4. Previously…

  5. Currently (320.220x293.355)

  6. Updated Transistor Count

  7. Updated Floorplan

  8. Layer MasksPoly

  9. Layer MasksMetal1

  10. Layer MasksMetal2

  11. Layer MasksMetal3

  12. Layer MasksMetal4

  13. Layout: Multiplier

  14. Layout: SRAM/Adder

  15. Layout: FinalText/Initial Permutation

  16. Layout: Mix Column/Rcon

  17. Layout: Key Expand

  18. Layout: SBOX

  19. Problems & Questions • Registers problematic • How can we make the chip smaller? • Re-doing many of the blocks, learn from previous mistakes. • Reset signal strength and buffer size needed for it. • White space reduction • Simulations take a long time.

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