1 / 17

Overall Project Objective:

Overall Project Objective: Design a Radio-Frequency indoor/outdoor navigation system, utilizing the existing wireless infrastructure. Design Stage Objective: LVS of all functional blocks.

dallon
Télécharger la présentation

Overall Project Objective:

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Overall Project Objective: Design a Radio-Frequency indoor/outdoor navigation system, utilizing the existing wireless infrastructure. Design Stage Objective: LVS of all functional blocks RF Triangulator: Indoor/Outdoor Location Finding18-525 Architecture ProposalGiovanni FonsecaDavid FuAmir GhitiStephen RoosDesign Manager: Myron Kwai

  2. Status Structural Verilog complete. Schematics completed. Layout of basic components complete. Major Layouts: ~90% done FPU: Done, adding buffering to strengthen signals Lookup: Done, testing Calc and Top Three: Finishing layouts Global routing still needs to be done

  3. Current Transistor counts • Total: 27,150 transistors* • Top Three: 6,500 trans. 3 x FPU Add/Sub Unit 1500 trans. Control Registers & Muxes: 2000 trans. • Calc: 17,950 trans. 2 x FPU Add/Sub Unit: 1500 trans. 1 x FPU Mult/Div Unit: ~5000 trans. 1 x Logshifter: 200 trans. 1 x Comparator: 800 transistors. FSM Logic: 850 transistors 25 x 12-bit M-S En Reg: 6600 trans. total 8-1,6-1,4-1,2-1 Mux Sets: 3000 trans. total • Lookup: 2,700 trans. Control Registers & Muxes: 2000 trans. Control Logic: 163 trans. • SRAM: 12k trans * count not including SRAM, with SRAM: ~38k

  4. Floorplan

  5. FPU Layouts Multiplication & Division Layout FASU Layout

  6. FPU Waveforms

  7. FPU Waveforms

  8. FPU Waveforms

  9. FPU Waveforms

  10. FPU Waveforms

  11. Lookup Layout

  12. Lookup Waveforms

  13. Lookup Waveforms

  14. Lookup Waveforms

  15. Lookup Waveforms

  16. Top Three Progress

  17. Questions/Concerns Large block simulations take a long time Much of Top Three still needs work

More Related