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The project aims to design an innovative radio-frequency navigation system for indoor and outdoor environments, leveraging existing wireless infrastructure. The design stage focuses on the low-level verification (LVS) of all functional blocks. Our multi-disciplinary team, including Giovanni Fonseca, David Fu, Amir Ghiti, and Stephen Roos, is led by design manager Myron Kwai. We have completed the structural Verilog, schematics, and layouts of basic components, achieving 90% completion on major layouts. Signal buffering is in progress, and testing of the lookup and calculation units is ongoing, with extensive details on transistor counts for different blocks provided.
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Overall Project Objective: Design a Radio-Frequency indoor/outdoor navigation system, utilizing the existing wireless infrastructure. Design Stage Objective: LVS of all functional blocks RF Triangulator: Indoor/Outdoor Location Finding18-525 Architecture ProposalGiovanni FonsecaDavid FuAmir GhitiStephen RoosDesign Manager: Myron Kwai
Status Structural Verilog complete. Schematics completed. Layout of basic components complete. Major Layouts: ~90% done FPU: Done, adding buffering to strengthen signals Lookup: Done, testing Calc and Top Three: Finishing layouts Global routing still needs to be done
Current Transistor counts • Total: 27,150 transistors* • Top Three: 6,500 trans. 3 x FPU Add/Sub Unit 1500 trans. Control Registers & Muxes: 2000 trans. • Calc: 17,950 trans. 2 x FPU Add/Sub Unit: 1500 trans. 1 x FPU Mult/Div Unit: ~5000 trans. 1 x Logshifter: 200 trans. 1 x Comparator: 800 transistors. FSM Logic: 850 transistors 25 x 12-bit M-S En Reg: 6600 trans. total 8-1,6-1,4-1,2-1 Mux Sets: 3000 trans. total • Lookup: 2,700 trans. Control Registers & Muxes: 2000 trans. Control Logic: 163 trans. • SRAM: 12k trans * count not including SRAM, with SRAM: ~38k
FPU Layouts Multiplication & Division Layout FASU Layout
Questions/Concerns Large block simulations take a long time Much of Top Three still needs work