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HBD/TPC Electronics Status

HBD/TPC Electronics Status. Works done to for Prototype detector readout Understand packing density and heat loading issues Address the overall system architecture How DCM will process such large data volume (400 optical fibers). HBD/TPD readout method. HBD:

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HBD/TPC Electronics Status

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  1. HBD/TPC Electronics Status Works done to for Prototype detector readout Understand packing density and heat loading issues Address the overall system architecture How DCM will process such large data volume (400 optical fibers)

  2. HBD/TPD readout method HBD: Preamp/shaper mounted on the pad plane. Signal will be driven to the edge of detector. We would like to measure T0 plus total charge. The longer shaping time will allow us to have several samples at the rising edge of the pulse. We will get 10-20 samples per signal per L1 trigger TPC: Short shaping time (~ 5 samples). 160 samples/channel/L1 trigger to cover 4 microsec drift time. The preamp + ADC + signal processing will be mounted near the detectors.

  3. Design issue • HBD will have preamp/shaper on the detector, the output signals will be driven to the edge of the detector, ~.1in per pair of signals • TPC pad size is 2mm by 1cm • We know the preamp/shaper has be a custom design • The signal processing (baseline subtraction, buffer zero suppression, buffer etc) is pure digital domain. • This can be done • We need to find a most economic way to get it done • For prototype one can use FPGA • ADC is the key components to be study. • It is complicated beast of analog+digital designs • It has lowest packing density and highest power per channel

  4. ADC • We have been looking for existing proof of multi-channel/low power ADC for a while. • We also spend a lots of time to understand these ADC • (thanks for medical imaging…) • We found • TI has 8 channel 40 MHz 12 bits ADC is 80 pins TQFP ( to be announced) • (100mw Multi-channel with serialized output (Nbits -> 2 wires) • per channel) • Analog device has • 4 channel 8 bits 65 MHz ADC (65mw/channel at 65MHz) • 4 channel 12 bits 50/65 MHz ADC (200mw/channel at 50MHZ • These two ADC are in chip scale package.

  5. The prototype board • We decide to use the TI 12bits ADC as the starting point. • A readout board configuration as • 8 8-channel ADC + an Altera Stratix FPGA (~1000 pin BGA) (signal processing) + optical chip set • The board should have about 6 “ wide. • The packing density should be reasonable to HBD. • Once we have a preamp/shaper to interface to we can progress further. (i.e. layout the test board)

  6. Signal processing • 8 8 channel ADC requires 8 sets of 8 channel of 480 mps differential LVDS receiver • An ALTERA STRATIX has chosen to interface to ADCs • The FPGA also server as • (code written) • Baseline subtraction • 160 samples(25ns/samples) 4 micro-sec L1 delay – 64 channels • Zero suppression • 5 Level 1 accepted event buffers – 64 channels • Data formatted for the readout • Serial download. • Receive relative timing signals ( L1 accept, Initialize) • (Additional code need to be written) • Test data/pattern • Control for the optical chip set • Busy logic + large event buffers due to zero suppression on the FEM.

  7. What we need to finish the board • Preamp/shaper chip • Who will do it • When can we have one can match the ADC • Find a connector for the TPC pad plane. • Have a preliminary pad plane signal routing examples for TPC • Funds • We will continue explore the possibility to get a custom chip with multi-channels commercial ADC core + our logics • This is done for ALICE TPC readout • It will be helpful to have consistent R&D fund that devotes to this effort

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