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USING TCAD TO MINIMIZE PROCESS DISPERSIONS

USING TCAD TO MINIMIZE PROCESS DISPERSIONS. G. DUBOIS D. ANDRADE. INTRODUCTION CALIBRATION RESULTS DIM PC PROCESS WINDOW SIMULATION RESULTS OTHER PROCESS CAUSES OF VARIATION COM BINED EFFECT OF PROCESS VARIATIONS CONCLUSION. A - INTRODUCTION

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USING TCAD TO MINIMIZE PROCESS DISPERSIONS

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  1. USING TCAD TO MINIMIZE PROCESS DISPERSIONS G. DUBOIS D. ANDRADE ALTIS Semiconductor Device Engineering team

  2. INTRODUCTION • CALIBRATION RESULTS • DIM PC PROCESS WINDOW SIMULATIONRESULTS • OTHER PROCESS CAUSES OF VARIATION • COMBINED EFFECT OF PROCESS VARIATIONS • CONCLUSION ALTIS Semiconductor Device Engineering team

  3. A - INTRODUCTION • The goal is to demonstrate that TCAD could be very useful • in identifying the process root causes of transistor electrical • parameters dispersion, mainly Ion , Vt and Ioff.The following • study was done on a 0.18µm designed gate length CMOS • process . ALTIS Semiconductor Device Engineering team

  4. DEVICES MENU ALTIS Semiconductor Device Engineering team

  5. B - CALIBRATION • PROCESS CALIBRATION: • Impurity diffusion, activation models and dislocation calibrationvariables were taken from INFINEON calibration work. • ELECTRICAL CALIBRATION : • Mobility model has been shared with INFINEON simulation group. • RESULTS : • I-V Characteristics end up very close to measurements performedon product. ALTIS Semiconductor Device Engineering team

  6. ALTIS Semiconductor Device Engineering team

  7. SOURCE DRAIN FET CHANNEL LENGTH ALTIS Semiconductor Device Engineering team

  8. Simulation properly matches product measurements. ALTIS Semiconductor Device Engineering team

  9. C – PC DIM PROCESS WINDOW SIMULATION ALTIS Semiconductor Device Engineering team

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  12. C – PC DIM PROCESS WINDOW SIMULATION • The simulation shows a good matching with « the real world ». • Halo implant tailoring allows to reduce the Ion (or Vt) spread, • due to PC DIM variation, within +/- 5 %. ALTIS Semiconductor Device Engineering team

  13. D - ANALYSIS OF OTHERCAUSES OF ELECTRICAL VARIATION • 1° VARIATION OF EXTENSION IMPLANT DUE TO SCREEN • OXIDE THICKNESS SPREAD. The extension implant being low energy, it is strongly influenced by screen oxide thickness variation… ALTIS Semiconductor Device Engineering team

  14. REMAINING Gox + SPACER 0 on Si SPACER 0 POLY ALTIS Semiconductor Device Engineering team

  15. TCAD simulation shows that: • A huge variation of remaining gate oxide induces a small variation of screen oxide. • Screen oxide thickness variation represents 50% of Spacer 0 (poly oxidation thickness) variation. • Consequently, the extension implant is not impacted by gate oxide, nor Spacer 0 fluctuations. ALTIS Semiconductor Device Engineering team

  16. 2° VARIATION OF ANNEALS TEMPERATURE Rapid Thermal Process single wafer tools, using infra red heating systems, may present slight temperature variations inducing wafer to wafer, and within wafer, spread. ALTIS Semiconductor Device Engineering team

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  18. E – COMBINED EFFECTS OF PROCESS VARIATIONS ALTIS Semiconductor Device Engineering team

  19. ALTIS Semiconductor Device Engineering team

  20. F – CONCLUSION TCAD simulation consists in a very efficient support for manufacturing engineers. It indeed provides an accurate sizing of the different processes effect. Only considering PC dim & T° anneal variations induces 85% of the devices electrical parameters total spread. Those twocomponents are the first order root causes of the total device electrical variation. ALTIS Semiconductor Device Engineering team

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