Elastic Circuits blending synchronous and asynchronous technologies

Elastic Circuitsblending synchronous and asynchronous technologies Jordi Cortadella Universitat Politècnica de Catalunya, Barcelona (joint work with M. Kishinevsky and M. Galceran-Oms) Collège de FranceMay 21st, 2013

… time is elastic … Elastic circuits

Synchronous circuit Flip Flops CombinationalLogic Flip Flops PLL Elastic circuits

Asynchronous circuit L CombinationalLogic L C C delay 4-phase Elastic circuits

Asynchronous circuit ReqIn ReqOut C C C C AckOut AckIn • David Muller’s pipeline (late 50’s) • Sutherland’s Micropipelines (Turing award, 1989) Elastic circuits

Globally-asynchronousLocally-synchronous GALS

SoC design with GALS • Most IPs are synchronous • Different components may have different operating frequencies • Some components have variable latencies (e.g., cache hit/miss latency) • Multiple clock domains are essential DSP P CLK3 Bridge Bridge CDC CDC Fast Bus CLK1 Mem CLK2 Slow Bus Elastic circuits

Multiple clock domains Independent clocks Rational clockfrequencies Single clock(mesochronous) CLK1 f1/f0 CLK (f0) f2/f0 CLK2 CLK0 CLK f3/f0 CLK3 (controllable skew) Elastic circuits

Synchronous handshakes Sender Receiver Data Valid Ack CLK1 CLK2 • The arrival of data is unpredictable • Handshakes solve the problem Elastic circuits

The problem: metastability D Q D Q CLKS CLKR setup hold CLKR D Q ? Elastic circuits

Metastability Source: W. J. Dally, Lecture notes for EE108A, Lecture 13.Metastability and Synchronization Failure (or When Good Flip-Flops go Bad) 11/9/2005. Elastic circuits

Metastability logic 0 logic 1 metastable Elastic circuits

Classical synchronous solution D Q D Q D Q D Q CLKT CLKR Mean Time Between Failures fФ: frequency of the clock fD: frequency of the data tr: resolve time available W: metastability window : resolve time constant Example Elastic circuits

Handshake with synchronizers Sender Receiver Data Valid Ack CLK1 CLK2 • Simple solution • Throughput can be highly degraded:a long round trip for every transaction Elastic circuits

Asynchronous FIFOs Circular buffer Data Data 3-4 cycles 1 cycle 1 cycle Valid Valid FIFO control Ack Ack Clk Out Clk In • Ack is issued as soon as data has been delivered • No impact on throughput (1 token/cycle) • Min latency determined by the internal synchronizers • Some tricky structures for the FIFO pointers (e.g. Grey encoding) Elastic circuits

SoC design with GALS • Bridges for Clock Domain Crossing usually contain asynchronous FIFOs • Latency cost only when interfacing with synchronous domains • No latency penalty between asynchronous domains DSP P CLK3 Bridge Bridge CDC CDC Fast Bus CLK1 Mem CLK2 Slow Bus Elastic circuits

Synchronous and Asynchronousmeeting each other

Meanwhile, a small village ofindomitable engineers was resisting the synchronous occupation … Asynchronia Elastic circuits

Bill Grundmann(Intel’s director of CAD research, Technical director for CAD technology for the Alpha Microprocessor): “The specification of a complex system is usuallyasynchronous (functional units, messages, queues, …), … however the clock appears when we move downto the implementation levels” (in a technical discussion about system designwithM. Kishinevskyand J. Cortadella, 2004) Elastic circuits

Async and Sync meeting each other Async • Modular (time elasticity) • But hard to analyze and synthesize J. O’Leary and G. Brown, 1997Synchronous emulation of asynchronous circuits A. Peetersand K. Van Berkel, 2001 Synchronous handshake circuits Elastic Circuits(Sync / Async) Cortadella et al., Desynchronization, 2003 L. Carloni et al., 1999A methodology for correct-by-construction latency-insensitive design • Easy to analyze and synthesize • Not modular (time rigid) Sync Elastic circuits

Different flavors of elasticity … … + Rigid 4 7 1 … 4 8 3 time … 0 1 2 … 4 + 7 1 a … 3 4 8 0 1 2 Asynchronous … 7 1 4 1 2 0 … + e … 8 4 3 Synchronous Elastic Elastic circuits

Why synchronous elasticity? • Time is discrete (cycle based), but unpredictable (unknown number of cycles) • Examples • Short/long integer addition (8 bits, 64 bits) • Floating-point units • Cache latency: fast hit(2), slow hit(3), miss(>20) • Bus arbitration • Latencies in Network-on-Chip • … and many others Elastic circuits

… even at design time Sender Receiver CLK Can we add a register without modifying the functionality of the system? Elastic circuits

Many systems are already elastic AMBA AXI bus protocol Handshake signals Elastic circuits

Designing withsynchronous elasticity

Communication channel sender receiver Data Data Long wires: slow transmission Elastic circuits

Pipelined communication Data sender receiver Data How about if the sender does not always send valid data? Elastic circuits

Pipelined communication Data sender receiver Data Elastic circuits

Pipelined communication Data sender receiver Data ??? Elastic circuits

The Valid bit sender receiver Data Data Valid Valid Elastic circuits

The Valid bit Data Valid sender receiver Data Valid Elastic circuits

The Valid bit Data Valid sender receiver Data Valid How about if the receiver is not always ready ? Elastic circuits

The Stop bit sender receiver Data Data Valid Valid Stop Stop 0 0 0 0 0 Elastic circuits

The Stop bit sender receiver Data Data Valid Valid Stop Stop 1 1 1 1 1 Back-pressure Elastic circuits

The Stop bit sender receiver Data Data Valid Valid Stop Stop 0 0 0 0 1 Long combinational path Elastic circuits

Relay stations (Carloni, 1999) sender receiver shell shell main main main pearl pearl aux aux aux Elastic circuits

Elastic Circuits blending synchronous and asynchronous technologies