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Asynchronous Sequential Circuits

Asynchronous Sequential Circuits. Asynch. vs. Synch. Asynchronous circuits don’t use clock pulses State transitions by changes in inputs Storage Elements: Clockless storage elements or Delay elements In many cases, as combinational feedback  Normally much harder to design.

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Asynchronous Sequential Circuits

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  1. Asynchronous SequentialCircuits

  2. Asynch. vs. Synch. • Asynchronous circuits don’t use clock pulses • State transitions by changes in inputs • Storage Elements: • Clockless storage elements or • Delay elements • In many cases, as combinational feedback •  Normally much harder to design

  3. Asynch. Sequential Circuit x1 z1 x2 z2 inputs outputs Combinational Circuit xn zm y1 Y1 Y2 Next State y2 Current State yk Yk delay delay delay

  4. Asynch. Sequential Circuit • yi = Yi in steady state (but may be different during transition) • Simultaneous change in two (or more) inputs is prohibited. • The time between two changes must be less than the time of stability.

  5. Advantages and Disadvantages • Advantages: • Low power • High performance • No need for clock • Disadvantages: • Complexity of design process

  6. Analysis • Find feedback loops and name feedback variables appropriately. • Find boolean expressions of Yi’s in terms of yi’s and inputs. y1 Y1 x y2 Y2 Y1 = x.y1 + x’.y2 Y2 = x.y1’ + x’.y2

  7. Analysis • Draw a map: • rows: yi’s • columns: inputs • entries: Yi’s x x x 0 1 0 1 0 1 y1 y2 y1 y2 y1 y2 00 0 0 00 0 1 00 00 01 01 1 01 1 01 11 0 1 01 11 1 11 0 11 10 1 1 11 10 10 10 0 1 0 0 00 10 Y1 = x.y1 + x’.y2 Y2 = x.y1’ + x’.y2 (Transition Table) Y1 Y2

  8. Analysis • To have a stable state, Y must be = y (circled) x 0 1 y1 y2 00 00 01 01 11 01 (Transition Table) Y1 Y2 11 10 11 10 00 10 • At y1y2x = 000, if x: 0  1 • then Y1Y2: 00  01 • then y1y2 = 01 (2nd row): stable

  9. Analysis • In general, if an input takes the circuit to an unstable state, yi’s change until a stable state is found. x 0 1 y1 y2 00 00 01 01 11 01 • General state of circuit: • y1y2x: • There are 4 stable states: • 000, 011, 110, 101 • and 4 unstable states. 11 10 11 10 00 10

  10. State Table • As synchronous: next state present state 00 01 10 11 00 01 11 01 00 10 11 10

  11. x 0 1 a a b b c b c d c d a d Flow Table • As Transition Table (but with symbolic states):

  12. x1 x2 00 11 10 01 a ,0 ,0 ,0 ,0 a a a b b ,0 ,0 ,1 ,0 a a b b Flow Table: Example 2 • Two states, two inputs, one output. • Each row has more than one stable state. • If x1 = 0, state is a. • If x1x2 = 00  x1x2 = 10, then state becomes b. • For x1x2 = 11, state is either a or b. • If previously in x1x2 = 01, keeps state a, • If previously in x1x2 = 10, keeps state b. • Reminder: cannot go from 00 to 11.

  13. x1 x2 00 11 10 01 a ,0 ,0 ,0 ,0 a a a b x1 x2 b ,0 ,0 ,1 ,0 a a b b 00 11 10 01 y 0 ,0 ,0 ,0 ,0 0 0 1 0 1 ,0 ,0 ,1 ,0 0 0 1 1 Circuit Design • From flow table to circuit: • Assign a unique binary value to each state, x1 x2 x1 x2 00 11 10 00 11 10 01 01 y y 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 1 Map for output z (=x1x2y) Map for Y (=x1x2’+x1y)

  14. Circuit Diagram z = x1x2y x1 Y x2 Y = x1x2’+x1y y

  15. Race Condition • If two (or more) state variables change in response to a change in an input, there is a race condition. • E.g. from 00 to 11, due to delays 00  01  11 OR 00  10  11. • Critical Race: • If final steady state depends on the order of changes in state vars.

  16. Race: Examples • Noncritical Cases: x x 0 1 0 1 y1y2 y1y2 00 00 11 00 00 11 01 01 11 01 11 11 11 01 10 10 11 11 00  11  01 00  11 00  01 00  01  11 00  10  11 00  10  11  01

  17. Race: Examples • Critical Cases: x x 0 1 0 1 y1y2 y1y2 00 00 11 00 00 11 01 01 11 01 11 11 11 11 10 10 10 10 00  11 00  11 00  01  11 00  01 00  10 00  10

  18. y x1 Y x2 Instability Y = (x1 y)’ x2 x1 x2 00 11 10 01 y • For x1x2 = 11, there is no steady state. •  Oscillation. • For x1x2 = 11, Y = y’  unstable. 0 0 1 1 0 1 0 0 0 1

  19. THE END

  20. x1 x2 00 11 10 01 a a b c a b b c a b c a c c c No-Race State Assignment • Must assign binary values to states such that: • one change in an input may not cause two changes in state variables. • because, due to delays, one of the variable change sooner and may stay in an unwanted stable state. • From a, if x1x2 = 10  11, must go to c and stay there. • But by the following assignment, it may go to b and stay there. 00 01 a b c 11 • a and b must be different in one bit, • a and c must be different in one bit.

  21. No-Race State Assignment • Impossible  add one more row. x1 x2 00 11 10 01 a a b d a b b c a b 00 01 a b d c c c c c a - - d • d is an intermediate (unstable) state. • - means any value can be assigned (Except d=10). c d 11 10

  22. x1 x2 00 11 10 01 00 01 a b a b a d a b a b d b a c c b c c d c c d d d 11 10 Example 2 • If there were no diagonal transition, it would be possible • Impossible  add some more rows.

  23. y1 y2 00 01 01 00 11 10 y3 a b 0 a b c g 1 f 0 e d c d 11 10 Example 2 x1 x2 00 11 10 01 a = 000 b a e a a b = 001 d b b • b is adjacent to a, c, d • c  a through g • a  d through e • d  c through f g c = 011 c b c g = 010 a - - - - 110 - - - - f = 111 c - c f f d = 101 d d - e = 100 - d -

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